component

SN74HC540PW

Public Made by Adom

by adom

Texas Instruments Inverters, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74hc540pwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
sn74hc540pw / README.md
History Download
Ray Publish 0.1.0 d941232 12d ago

SN74HC540PW

Texas Instruments · Inverters · TSSOP-20

SN74HC540PW from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low output-enable 1; if either OE1 or OE2 is high, all eight outputs are in the high-impedance state.
2 A1 input Data input 1, inverted at output Y1; unused inputs must be held at VCC or GND.
3 A2 input Data input 2, inverted at output Y2; unused inputs must be held at VCC or GND.
4 A3 input Data input 3, inverted at output Y3; unused inputs must be held at VCC or GND.
5 A4 input Data input 4, inverted at output Y4; unused inputs must be held at VCC or GND.
6 A5 input Data input 5, inverted at output Y5; unused inputs must be held at VCC or GND.
7 A6 input Data input 6, inverted at output Y6; unused inputs must be held at VCC or GND.
8 A7 input Data input 7, inverted at output Y7; unused inputs must be held at VCC or GND.
9 A8 input Data input 8, inverted at output Y8; unused inputs must be held at VCC or GND.
10 GND power_in Ground reference for the device.
11 Y8 tri_state 3-state inverted output for A8 with ±6-mA drive at 5 V; high-impedance when OE1 or OE2 is high.
12 Y7 tri_state 3-state inverted output for A7 with ±6-mA drive at 5 V; high-impedance when OE1 or OE2 is high.
13 Y6 tri_state 3-state inverted output for A6 with ±6-mA drive at 5 V; high-impedance when OE1 or OE2 is high.
14 Y5 tri_state 3-state inverted output for A5 with ±6-mA drive at 5 V; high-impedance when OE1 or OE2 is high.
15 Y4 tri_state 3-state inverted output for A4 with ±6-mA drive at 5 V; high-impedance when OE1 or OE2 is high.
16 Y3 tri_state 3-state inverted output for A3 with ±6-mA drive at 5 V; high-impedance when OE1 or OE2 is high.
17 Y2 tri_state 3-state inverted output for A2 with ±6-mA drive at 5 V; high-impedance when OE1 or OE2 is high.
18 Y1 tri_state 3-state inverted output for A1 with ±6-mA drive at 5 V; high-impedance when OE1 or OE2 is high.
19 OE2 input Active-low output-enable 2; if either OE1 or OE2 is high, all eight outputs are in the high-impedance state.
20 VCC power_in Supply voltage, 2 V to 6 V recommended, with a 0.1-μF bypass capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HC540PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hc540pw-etched.step / sn74hc540pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc540pw.step / sn74hc540pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 ae0e4a4e25a26926, retrieved 2026-10-10, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF