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Contents

README

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SN74HC540

Texas Instruments · Buffer / Line Driver · SOIC-20

The SN74HC540 is an octal inverting buffer and line driver with 3-state outputs. Its inputs and outputs sit on opposite sides for a flow-through layout, and two active-low output-enables gate all eight buffers. Each output is the inverse of its input, useful for driving buses while inverting.

Pinout

Pin Name Type Function
1 OE1 input Active-low output-enable 1. NORed with OE2; when either OE input is high, all Y outputs are in high-impedance state.
2 A1 input Data input for channel 1. CMOS logic input; drives inverted output Y1 when device is enabled.
3 A2 input Data input for channel 2. Drives inverted output Y2 when device is enabled.
4 A3 input Data input for channel 3. Drives inverted output Y3 when device is enabled.
5 A4 input Data input for channel 4. Drives inverted output Y4 when device is enabled.
6 A5 input Data input for channel 5. Drives inverted output Y5 when device is enabled.
7 A6 input Data input for channel 6. Drives inverted output Y6 when device is enabled.
8 A7 input Data input for channel 7. Drives inverted output Y7 when device is enabled.
9 A8 input Data input for channel 8. Drives inverted output Y8 when device is enabled.
10 GND power_in Ground reference (0 V). Return for VCC supply current and CMOS input/output logic levels.
11 Y8 tri_state 3-state inverted output for channel 8. High-current CMOS driver, ±6 mA at 5 V; drives up to 15 LSTTL loads. High-Z when either OE1 or OE2 is high.
12 Y7 tri_state 3-state inverted output for channel 7. High-current CMOS driver, ±6 mA at 5 V. High-Z when either OE1 or OE2 is high.
13 Y6 tri_state 3-state inverted output for channel 6. High-current CMOS driver, ±6 mA at 5 V. High-Z when either OE1 or OE2 is high.
14 Y5 tri_state 3-state inverted output for channel 5. High-current CMOS driver, ±6 mA at 5 V. High-Z when either OE1 or OE2 is high.
15 Y4 tri_state 3-state inverted output for channel 4. High-current CMOS driver, ±6 mA at 5 V. High-Z when either OE1 or OE2 is high.
16 Y3 tri_state 3-state inverted output for channel 3. High-current CMOS driver, ±6 mA at 5 V. High-Z when either OE1 or OE2 is high.
17 Y2 tri_state 3-state inverted output for channel 2. High-current CMOS driver, ±6 mA at 5 V. High-Z when either OE1 or OE2 is high.
18 Y1 tri_state 3-state inverted output for channel 1. High-current CMOS driver, ±6 mA at 5 V. High-Z when either OE1 or OE2 is high.
19 OE2 input Active-low output-enable 2. NORed with OE1; when either OE input is high, all Y outputs are in high-impedance state.
20 VCC power_in Positive supply, 2 V to 6 V recommended (absolute max 7 V). Bypass with 0.1 µF (optionally paralleled with 1 µF) placed close to the pin.

Key specifications

Parameter Value
Type Octal inverting buffer / line driver, 3-state
Logic family 74HC (CMOS)
Configuration 8 inverting buffers, flow-through pinout
Supply voltage 2 V to 6 V
Output current +-6 mA at VCC = 4.5 V
Propagation delay 14 ns typ at 5 V
Operating temperature -40 C to 85 C

Ordering variants

Same part, different packaging or reel option.

  • SN74HC540DW
  • SN74HC540N
  • SN74HC540NS
  • SN74HC540NSR
  • SN74HC540PW
  • SN74HC540J
  • SN74HC540FK

CAD (KiCad official)

  • Symbol: sn74hc540.kicad_sym
  • Footprint: sn74hc540.kicad_mod
  • 3D model: SOIC-20 wide body from KiCad Package_SO/SOIC-20W_7.5x12.8mm_P1.27mm.
  • 3D model files: sn74hc540-etched.step / sn74hc540-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc540.step / sn74hc540.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 d54581bf2a2bec36, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF