# SN74HC4040DR

**lingxingic** · Counters, Dividers · SOP-16

SN74HC4040DR from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q11 | output | Parallel binary counter output Q11 of the 12-stage ripple counter (output 11). |
| 2 | Q5 | output | Parallel binary counter output Q5 (output 5) of the 12-stage ripple counter. |
| 3 | Q4 | output | Parallel binary counter output Q4 (output 4) of the 12-stage ripple counter. |
| 4 | Q6 | output | Parallel binary counter output Q6 (output 6) of the 12-stage ripple counter. |
| 5 | Q3 | output | Parallel binary counter output Q3 (output 3) of the 12-stage ripple counter. |
| 6 | Q2 | output | Parallel binary counter output Q2 (output 2) of the 12-stage ripple counter. |
| 7 | Q1 | output | Parallel binary counter output Q1 (output 1) of the 12-stage ripple counter. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | Q0 | output | Parallel binary counter output Q0 (output 0), the first stage of the ripple counter. |
| 10 | CP | input | Clock input; the counter advances on the HIGH-to-LOW (falling) edge of CP. |
| 11 | MR | input | Master reset input, active HIGH; when HIGH it resets Q0 to Q11 to LOW, overriding the clock. |
| 12 | Q8 | output | Parallel binary counter output Q8 (output 8) of the 12-stage ripple counter. |
| 13 | Q7 | output | Parallel binary counter output Q7 (output 7) of the 12-stage ripple counter. |
| 14 | Q9 | output | Parallel binary counter output Q9 (output 9) of the 12-stage ripple counter. |
| 15 | Q10 | output | Parallel binary counter output Q10 (output 10) of the 12-stage ripple counter. |
| 16 | VCC | power_in | Positive supply voltage; recommended operating range is 2.0 V to 6.0 V for the HC family and 4.5 V to 5.5 V for the HCT family. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Recommended supply voltage | VCC | 2 | 5 | 6 | V |  | 8 |
| Recommended input voltage | VI | 0 |  |  | V | max printed as VCC | 8 |
| Recommended output voltage | VO | 0 |  |  | V | max printed as VCC | 8 |
| Recommended ambient temperature | Tamb | -40 |  | 125 | ℃ |  | 8 |
| Absolute max supply voltage | VCC | -0.5 |  | 7 | V |  | 8 |
| Absolute max input clamping current | IIK | -20 |  | 20 | mA | VI<-0.5V or VI>VCC+0.5V | 8 |
| Absolute max output clamping current | IOK | -20 |  | 20 | mA | VI<-0.5V or VI>VCC+0.5V | 8 |
| Absolute max output current | IO | -25 |  | 25 | mA | 0.5V<VO<VCC+0.5V | 8 |
| Absolute max supply current | ICC | -50 |  | 50 | mA |  | 8 |
| Absolute max ground current | IGND | -50 |  | 50 | mA |  | 8 |
| Storage temperature | Tstg | -65 |  | 150 | ℃ |  | 8 |
| Soldering temperature (SOP/TSSOP) | TL |  |  | 260 | ℃ | 10s; SOP/TSSOP | 8 |
| HIGH-level input voltage | VIH | 1.5 |  |  | V | VCC=2.0V | 11 |
| HIGH-level input voltage | VIH | 3.15 |  |  | V | VCC=4.5V | 11 |
| HIGH-level input voltage | VIH | 4.2 |  |  | V | VCC=6.0V | 11 |
| LOW-level input voltage | VIL |  |  | 0.5 | V | VCC=2.0V | 11 |
| LOW-level input voltage | VIL |  |  | 1.35 | V | VCC=4.5V | 11 |
| LOW-level input voltage | VIL |  |  | 1.8 | V | VCC=6.0V | 11 |
| HIGH-level output voltage | VOH | 1.9 |  |  | V | VI=VIH or VIL; IO=-20uA; VCC=2.0V | 11 |
| HIGH-level output voltage | VOH | 4.4 |  |  | V | VI=VIH or VIL; IO=-20uA; VCC=4.5V | 11 |
| HIGH-level output voltage | VOH | 5.9 |  |  | V | VI=VIH or VIL; IO=-20uA; VCC=6.0V | 11 |
| HIGH-level output voltage | VOH | 3.7 |  |  | V | VI=VIH or VIL; IO=-4.0mA; VCC=4.5V | 11 |
| HIGH-level output voltage | VOH | 5.2 |  |  | V | VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 11 |
| LOW-level output voltage | VOL |  |  | 0.1 | V | VI=VIH or VIL; IO=20uA; VCC=2.0V | 11 |
| LOW-level output voltage | VOL |  |  | 0.4 | V | VI=VIH or VIL; IO=4.0mA; VCC=4.5V | 11 |
| Input leakage current | II | -1 |  | 1 | uA | VI=VCC or GND; VCC=6.0V | 11 |
| Supply current | ICC |  |  | 160 | uA | VI=VCC or GND; IO=0A; VCC=6.0V | 11 |
| propagation delay CP to Q0 | tpd |  |  | 225 | ns | VCC=2.0V; CP to Q0; see Figure 4 | 14 |
| propagation delay CP to Q0 | tpd |  |  | 45 | ns | VCC=4.5V; CP to Q0; see Figure 4 | 14 |
| propagation delay CP to Q0 | tpd |  |  | 38 | ns | VCC=6.0V; CP to Q0; see Figure 4 | 14 |
| propagation delay Qn to Qn+1 | tpd |  |  | 150 | ns | VCC=2.0V; Qn to Qn+1; see Figure 4 | 14 |
| propagation delay Qn to Qn+1 | tpd |  |  | 30 | ns | VCC=4.5V; Qn to Qn+1; see Figure 4 | 14 |
| propagation delay Qn to Qn+1 | tpd |  |  | 26 | ns | VCC=6.0V; Qn to Qn+1; see Figure 4 | 14 |
| HIGH to LOW propagation delay MR to Qn | tPHL |  |  | 280 | ns | VCC=2.0V; MR to Qn; see Figure 4 | 14 |
| HIGH to LOW propagation delay MR to Qn | tPHL |  |  | 56 | ns | VCC=4.5V; MR to Qn; see Figure 4 | 14 |
| HIGH to LOW propagation delay MR to Qn | tPHL |  |  | 48 | ns | VCC=6.0V; MR to Qn; see Figure 4 | 14 |
| transition time Qn | tt |  |  | 110 | ns | VCC=2.0V; Qn; see Figure 4 | 14 |
| transition time Qn | tt |  |  | 22 | ns | VCC=4.5V; Qn; see Figure 4 | 14 |
| transition time Qn | tt |  |  | 19 | ns | VCC=6.0V; Qn; see Figure 4 | 14 |
| pulse width CP input HIGH or LOW | tW | 120 |  |  | ns | VCC=2.0V; CP input HIGH or LOW; see Figure 4 | 14 |
| pulse width CP input HIGH or LOW | tW | 24 |  |  | ns | VCC=4.5V; CP input HIGH or LOW; see Figure 4 | 14 |
| pulse width CP input HIGH or LOW | tW | 20 |  |  | ns | VCC=6.0V; CP input HIGH or LOW; see Figure 4 | 14 |
| pulse width MR input HIGH | tW | 120 |  |  | ns | VCC=2.0V; MR input HIGH; see Figure 4 | 14 |
| pulse width MR input HIGH | tW | 24 |  |  | ns | VCC=4.5V; MR input HIGH; see Figure 4 | 14 |
| pulse width MR input HIGH | tW | 20 |  |  | ns | VCC=6.0V; MR input HIGH; see Figure 4 | 14 |
| recovery time MR to CP | trec | 75 |  |  | ns | VCC=2.0V; MR to CP; see Figure 4 | 14 |
| recovery time MR to CP | trec | 15 |  |  | ns | VCC=4.5V; MR to CP; see Figure 4 | 14 |
| recovery time MR to CP | trec | 13 |  |  | ns | VCC=6.0V; MR to CP; see Figure 4 | 14 |
| maximum frequency CP input | fmax | 4 |  |  | MHz | VCC=2.0V; CP input; see Figure 4 | 14 |
| maximum frequency CP input | fmax | 20 |  |  | MHz | VCC=4.5V; CP input; see Figure 4 | 14 |
| maximum frequency CP input | fmax | 24 |  |  | MHz | VCC=6.0V; CP input; see Figure 4 | 14 |

## CAD (KiCad official)

- Symbol: `SN74HC4040DR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hc4040dr-etched.step` / `sn74hc4040dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc4040dr.step` / `sn74hc4040dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [lingxingic datasheet](docs/sn74hc4040dr-datasheet.pdf) (20 pp, sha256 `4a53348bd76eea5e`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74hc4040dr-datasheet.pdf)