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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	11d ago
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page.json	Set visibility: public · Ray	11d ago
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sn74hc4040dbr-etched.glb	sn74hc4040dbr: factory component page (tier=lcsc) · Ray	11d ago
sn74hc4040dbr-etched.step	sn74hc4040dbr: factory component page (tier=lcsc) · Ray	11d ago
sn74hc4040dbr-hero.glb	sn74hc4040dbr: hero GLB from the etched model (keeps the MPN mark) · Ray	11d ago
sn74hc4040dbr-hero.overlay.json	Publish 0.1.0 · Ray	11d ago
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sn74hc4040dbr.lbr	Publish 0.1.0 · Ray	11d ago
sn74hc4040dbr.step	Publish 0.1.0 · Ray	11d ago

SN74HC4040DBR

Texas Instruments · Counters, Dividers · SSOP-16-208mil

SN74HC4040DBR from Texas Instruments, in a SSOP-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	QL	output	Counter stage 12 output; counter advances on high-to-low CLK transition, drives up to 10 LSTTL loads, ±4 mA at 5 V.
2	QF	output	Counter stage 6 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
3	QE	output	Counter stage 5 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
4	QG	output	Counter stage 7 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
5	QD	output	Counter stage 4 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
6	QC	output	Counter stage 3 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
7	QB	output	Counter stage 2 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
8	GND	power_in	Ground; continuous current through VCC or GND is limited to ±50 mA.
9	QA	output	Counter stage 1 output (first stage, tpd from CLK typically 16 ns at 4.5 V); drives up to 10 LSTTL loads.
10	CLK	input	Clock input; count advances on a high-to-low transition, max clock frequency 22 MHz at 4.5 V for SN74HC4040.
11	CLR	input	Asynchronous clear; a high level resets the counter and sets all outputs low, minimum pulse width 18 ns at 4.5 V.
12	QI	output	Counter stage 9 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
13	QH	output	Counter stage 8 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
14	QJ	output	Counter stage 10 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
15	QK	output	Counter stage 11 output; drives up to 10 LSTTL loads, ±4 mA at 5 V.
16	VCC	power_in	Supply voltage, 2 V to 6 V recommended (absolute max 7 V); bypass with a 0.1-µF capacitor close to the pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SSOP-16-208mil
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: SN74HC4040DBR
Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
3D model: SSOP-16-208mil (KiCad packages3D, STEP)
3D model files: sn74hc4040dbr-etched.step / sn74hc4040dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc4040dbr.step / sn74hc4040dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 864adadf9c12e530, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF