SN74HC4040

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74hc4040",
  "title": "SN74HC4040",
  "brief": "TI 12-stage binary ripple counter, SOIC-16. Twelve outputs, clock + async clear, divides by up to 4096. Datasheet-verified.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "counter",
    "binary-counter",
    "ripple-counter",
    "74hc",
    "soic-16",
    "texas-instruments"
  ],
  "component": {
    "mpn": "SN74HC4040",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic IC",
    "subcategory": "12-stage binary ripple counter",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc4040.pdf",
    "parts": {
      "symbol": "sn74hc4040.kicad_sym",
      "footprint": "sn74hc4040.kicad_mod",
      "model_3d": "sn74hc4040-etched.glb",
      "model_3d_plain": "sn74hc4040.glb",
      "lbr": "sn74hc4040.lbr",
      "model_3d_step": "sn74hc4040-etched.step",
      "model_3d_step_plain": "sn74hc4040.step"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "QL",
        "type": "output",
        "description": "Counter stage 12 output (Q12, MSB). Push-pull CMOS output, ±4 mA drive at 5 V. Toggles on the falling edge of stage 11's output; frequency = fCLK / 4096."
      },
      {
        "number": "2",
        "name": "QF",
        "type": "output",
        "description": "Counter stage 6 output (Q6). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 64."
      },
      {
        "number": "3",
        "name": "QE",
        "type": "output",
        "description": "Counter stage 5 output (Q5). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 32."
      },
      {
        "number": "4",
        "name": "QG",
        "type": "output",
        "description": "Counter stage 7 output (Q7). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 128."
      },
      {
        "number": "5",
        "name": "QD",
        "type": "output",
        "description": "Counter stage 4 output (Q4). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 16."
      },
      {
        "number": "6",
        "name": "QC",
        "type": "output",
        "description": "Counter stage 3 output (Q3). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 8."
      },
      {
        "number": "7",
        "name": "QB",
        "type": "output",
        "description": "Counter stage 2 output (Q2). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 4."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground / negative supply return. 0 V reference for VCC and all logic levels."
      },
      {
        "number": "9",
        "name": "QA",
        "type": "output",
        "description": "Counter stage 1 output (Q1, LSB). Push-pull CMOS output, ±4 mA drive at 5 V. Toggles on each falling edge of CLK; frequency = fCLK / 2."
      },
      {
        "number": "10",
        "name": "CLK",
        "type": "input",
        "description": "Clock input. Counter advances on the high-to-low (falling-edge) transition. Standard CMOS logic input: VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Max clock frequency = 25 MHz at VCC = 6 V."
      },
      {
        "number": "11",
        "name": "CLR",
        "type": "input",
        "description": "Asynchronous master reset (active high). A high level asynchronously clears the counter and forces all Q outputs low, independent of CLK. Standard CMOS logic input."
      },
      {
        "number": "12",
        "name": "QI",
        "type": "output",
        "description": "Counter stage 9 output (Q9). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 512."
      },
      {
        "number": "13",
        "name": "QH",
        "type": "output",
        "description": "Counter stage 8 output (Q8). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 256."
      },
      {
        "number": "14",
        "name": "QJ",
        "type": "output",
        "description": "Counter stage 10 output (Q10). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 1024."
      },
      {
        "number": "15",
        "name": "QK",
        "type": "output",
        "description": "Counter stage 11 output (Q11). Push-pull CMOS output, ±4 mA drive at 5 V. Frequency = fCLK / 2048."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply input. Operating range 2 V to 6 V (absolute max 7 V). Bypass with a 0.1 µF ceramic close to the pin; a paralleled 1 µF is also recommended. ICC ≤ 80 µA (74HC) with static inputs."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74hc4040.pdf",
        "pages": 31,
        "sha256": "ad1231c1bceb2364",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74HC4040",
      "logic_family": "74HC",
      "function_code": "4040",
      "function_class": "Counter",
      "function_name": "12-Bit Binary Counter",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "sn74hc4040.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74hc4040-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "ba36a31a5f7e39fe78de13f00dcb40aa2d52c8a16429170b17e8f28556f8bfe0",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Type": "12-stage binary ripple counter",
      "Outputs": "12 (QA-QL, powers of two)",
      "Division": "divide-by-2 up to divide-by-4096",
      "Clock": "negative-edge triggered",
      "Reset": "asynchronous clear (active-high)",
      "Logic family": "HC (high-speed CMOS)",
      "Supply voltage": "2-6 V",
      "Package": "SOIC-16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74hc4040",
    "74hc4040",
    "12-stage counter",
    "binary ripple counter",
    "frequency divider",
    "cd4040"
  ],
  "discovery_pitch": "SN74HC4040 12-stage binary ripple counter (SOIC-16) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "sn74hc4040.kicad_sym",
    "sn74hc4040.kicad_mod",
    "sn74hc4040.glb",
    "sn74hc4040.lbr",
    "docs/hero.png",
    "docs/sn74hc4040-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "sn74hc4040-etched.step"
  ],
  "variants": [
    {
      "mpn": "SN74HC4040D (SOIC-16, tube)",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC4040DR (SOIC-16, tape & reel)",
      "kind": "packaging"
    }
  ]
}