# SN74HC4020N

**Texas Instruments** · Counters / Dividers · PDIP-16

SN74HC4020N from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QL | output | Counter output QL (stage 12 of the 14-stage ripple counter), driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 2 | QM | output | Counter output QM (stage 13 of the 14-stage ripple counter), driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 3 | QN | output | Counter output QN (stage 14, last stage of the ripple counter), driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 4 | QF | output | Counter output QF, driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 5 | QE | output | Counter output QE, driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 6 | QG | output | Counter output QG, driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 7 | QD | output | Counter output QD, driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | QA | output | Counter output QA (first stage), driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 10 | CLK | input | Clock input; the counter advances on the negative-going (falling) edge of the clock pulse. |
| 11 | CLR | input | Clear input; when high it resets all outputs low independently of the clock. |
| 12 | QI | output | Counter output QI, driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 13 | QH | output | Counter output QH, driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 14 | QJ | output | Counter output QJ, driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 15 | QK | output | Counter output QK, driving up to 10 LSTTL loads with ±4 mA drive at 5 V. |
| 16 | VCC | power_in | Supply voltage, 2 V to 6 V recommended, with a 0.1-µF bypass capacitor placed close to the pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-16 |
| Category | Logic ICs |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input hold current | II | -1000 |  | 1000 | nA | VI = VCC or 0; VCC = 6 V | 5 |
| Supply current | ICC |  |  | 80 | µA | VI = VCC or 0; IO = 0; VCC = 6 V | 5 |
| Input capacitance | Ci |  |  | 10 | pF | VCC = 2 to 6 V | 5 |
| High-level output voltage | VOH | 1.9 |  |  | V | IOH = -20 μA; VCC = 2 V | 5 |
| High-level output voltage | VOH | 4.4 |  |  | V | IOH = -20 μA; VCC = 4.5 V | 5 |
| High-level output voltage | VOH | 5.9 |  |  | V | IOH = -20 μA; VCC = 6 V | 5 |
| High-level output voltage | VOH | 3.84 |  |  | V | IOH = -4 mA; VCC = 4.5 V | 5 |
| High-level output voltage | VOH | 5.34 |  |  | V | IOH = -5.2 mA; VCC = 6 V | 5 |
| Low-level output voltage | VOL |  |  | 0.1 | V | IOL = 20 μA; VCC = 2 V | 5 |
| Low-level output voltage | VOL |  |  | 0.33 | V | IOL = 4 mA; VCC = 4.5 V | 5 |
| Supply voltage | VCC | 2 | 5 | 6 | V |  | 4 |
| High-level input voltage | VIH | 1.5 |  |  | V | VCC = 2 V | 4 |
| High-level input voltage | VIH | 3.15 |  |  | V | VCC = 4.5 V | 4 |
| High-level input voltage | VIH | 4.2 |  |  | V | VCC = 6 V | 4 |
| Low-level input voltage | VIL |  |  | 0.5 | V | VCC = 2 V | 4 |
| Low-level input voltage | VIL |  |  | 1.35 | V | VCC = 4.5 V | 4 |
| Low-level input voltage | VIL |  |  | 1.8 | V | VCC = 6 V | 4 |
| Input voltage | VI | 0 |  |  | V | Upper limit printed as VCC | 4 |
| Output voltage | VO | 0 |  |  | V | Upper limit printed as VCC | 4 |
| Input transition rise/fall time | tt |  |  | 1000 | ns | VCC = 2 V | 4 |
| Input transition rise/fall time | tt |  |  | 500 | ns | VCC = 4.5 V | 4 |
| Input transition rise/fall time | tt |  |  | 400 | ns | VCC = 6 V | 4 |
| Operating free-air temperature | TA | -40 |  | 85 | °C | SN74HC4020 catalog variant | 4 |
| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 4 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 or VI > VCC | 4 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VCC | 4 |
| Continuous output current | IO | -25 |  | 25 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND |  | -50 |  | 50 | mA |  | 4 |
| Junction temperature | TJ |  |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Clock frequency | fCLK | 4.3 |  |  | MHz | VCC = 2 V | 5 |
| Clock frequency | fCLK | 22 |  |  | MHz | VCC = 4.5 V | 5 |
| Clock frequency | fCLK | 25 |  |  | MHz | VCC = 6 V | 5 |
| Pulse duration CLK high or low | tW | 115 |  |  | ns | VCC = 2 V | 5 |
| Pulse duration CLK high or low | tW | 23 |  |  | ns | VCC = 4.5 V | 5 |
| Pulse duration CLK high or low | tW | 20 |  |  | ns | VCC = 6 V | 5 |
| Pulse duration CLR high | tW | 90 |  |  | ns | VCC = 2 V | 5 |
| Pulse duration CLR high | tW | 18 |  |  | ns | VCC = 4.5 V | 5 |
| Pulse duration CLR high | tW | 25 |  |  | ns | VCC = 6 V | 5 |
| Setup time, CLR inactive before CLK↓ | tsu | 75 |  |  | ns | VCC = 2 V | 5 |
| Setup time, CLR inactive before CLK↓ | tsu | 15 |  |  | ns | VCC = 4.5 V | 5 |
| Setup time, CLR inactive before CLK↓ | tsu | 13 |  |  | ns | VCC = 6 V | 5 |
| Maximum clock frequency (switching table) | fmax | 4.3 |  |  | ns | CL = 50 pF; VCC = 2 V | 6 |
| Maximum clock frequency (switching table) | fmax | 22 |  |  | ns | CL = 50 pF; VCC = 4.5 V | 6 |
| Maximum clock frequency (switching table) | fmax | 25 |  |  | ns | CL = 50 pF; VCC = 6 V | 6 |
| Propagation delay CLK to QA | tpd |  |  | 190 | ns | CL = 50 pF; VCC = 2 V | 6 |
| Propagation delay CLK to QA | tpd |  |  | 38 | ns | CL = 50 pF; VCC = 4.5 V | 6 |
| Propagation delay CLK to QA | tpd |  |  | 32 | ns | CL = 50 pF; VCC = 6 V | 6 |
| Propagation delay CLR to Any output | tPHL |  |  | 175 | ns | CL = 50 pF; VCC = 2 V | 6 |
| Propagation delay CLR to Any output | tPHL |  |  | 35 | ns | CL = 50 pF; VCC = 4.5 V | 6 |
| Propagation delay CLR to Any output | tPHL |  |  | 30 | ns | CL = 50 pF; VCC = 6 V | 6 |
| Output transition time | tt |  |  | 95 | ns | CL = 50 pF; VCC = 2 V | 6 |
| Output transition time | tt |  |  | 19 | ns | CL = 50 pF; VCC = 4.5 V | 6 |
| Output transition time | tt |  |  | 16 | ns | CL = 50 pF; VCC = 6 V | 6 |
| Junction-to-ambient thermal resistance (PDIP, N) | RθJA |  | 67 |  | °C/W | N (PDIP) 16-pin package | 4 |

## CAD (KiCad official)

- Symbol: `SN74HC4020N`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hc4020n-etched.step` / `sn74hc4020n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc4020n.step` / `sn74hc4020n.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74hc4020.pdf) (28 pp, sha256 `5425977e0f81754f`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74hc4020n-datasheet.pdf)