SN74HC393

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74hc393",
  "title": "SN74HC393",
  "brief": "TI dual 4-bit binary ripple counter, SOIC-14. Two counters, clock + clear each, cascadable. HC CMOS 2-6 V. Datasheet-verified.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "counter",
    "binary-counter",
    "74hc",
    "soic-14",
    "texas-instruments"
  ],
  "component": {
    "mpn": "SN74HC393",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic IC",
    "subcategory": "Dual 4-bit binary counter",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc393.pdf",
    "parts": {
      "symbol": "sn74hc393.kicad_sym",
      "footprint": "sn74hc393.kicad_mod",
      "model_3d": "sn74hc393-etched.glb",
      "model_3d_plain": "sn74hc393.glb",
      "lbr": "sn74hc393.lbr",
      "model_3d_step": "sn74hc393-etched.step",
      "model_3d_step_plain": "sn74hc393.step"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "1CLK",
        "type": "input",
        "description": "Counter 1 clock input. Counter 1 advances on the high-to-low (falling-edge) transition of this input. CMOS-level input, 2 V to 6 V logic swing; typical clock frequency 31 MHz at VCC=4.5 V."
      },
      {
        "number": "2",
        "name": "1CLR",
        "type": "input",
        "description": "Counter 1 asynchronous clear input, active high. When held high, Q1A-Q1D are forced low regardless of 1CLK. Minimum high pulse width ~16 ns at VCC=4.5 V."
      },
      {
        "number": "3",
        "name": "1QA",
        "type": "output",
        "description": "Counter 1 stage A (LSB) output. Toggles on each falling edge of 1CLK; divides input clock by 2. Push-pull CMOS output, ±4 mA drive at VCC=5 V."
      },
      {
        "number": "4",
        "name": "1QB",
        "type": "output",
        "description": "Counter 1 stage B output. Toggles on each falling edge of 1QA; divides 1CLK by 4. Push-pull CMOS output, ±4 mA drive at VCC=5 V."
      },
      {
        "number": "5",
        "name": "1QC",
        "type": "output",
        "description": "Counter 1 stage C output. Toggles on each falling edge of 1QB; divides 1CLK by 8. Push-pull CMOS output, ±4 mA drive at VCC=5 V."
      },
      {
        "number": "6",
        "name": "1QD",
        "type": "output",
        "description": "Counter 1 stage D (MSB) output. Toggles on each falling edge of 1QC; divides 1CLK by 16. Push-pull CMOS output, ±4 mA drive at VCC=5 V."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). Return path for VCC current."
      },
      {
        "number": "8",
        "name": "2QD",
        "type": "output",
        "description": "Counter 2 stage D (MSB) output. Toggles on each falling edge of 2QC; divides 2CLK by 16. Push-pull CMOS output, ±4 mA drive at VCC=5 V."
      },
      {
        "number": "9",
        "name": "2QC",
        "type": "output",
        "description": "Counter 2 stage C output. Toggles on each falling edge of 2QB; divides 2CLK by 8. Push-pull CMOS output, ±4 mA drive at VCC=5 V."
      },
      {
        "number": "10",
        "name": "2QB",
        "type": "output",
        "description": "Counter 2 stage B output. Toggles on each falling edge of 2QA; divides 2CLK by 4. Push-pull CMOS output, ±4 mA drive at VCC=5 V."
      },
      {
        "number": "11",
        "name": "2QA",
        "type": "output",
        "description": "Counter 2 stage A (LSB) output. Toggles on each falling edge of 2CLK; divides input clock by 2. Push-pull CMOS output, ±4 mA drive at VCC=5 V."
      },
      {
        "number": "12",
        "name": "2CLR",
        "type": "input",
        "description": "Counter 2 asynchronous clear input, active high. When held high, Q2A-Q2D are forced low regardless of 2CLK. Minimum high pulse width ~16 ns at VCC=4.5 V."
      },
      {
        "number": "13",
        "name": "2CLK",
        "type": "input",
        "description": "Counter 2 clock input. Counter 2 advances on the high-to-low (falling-edge) transition of this input. CMOS-level input, 2 V to 6 V logic swing."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply. Recommended 2 V to 6 V (5 V nominal). Bypass to GND with 0.1 µF (and optional 1 µF) placed close to the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74hc393.pdf",
        "pages": 38,
        "sha256": "aa77c46be80d7142",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74HC393",
      "logic_family": "74HC",
      "function_code": "393",
      "function_class": "Counter",
      "function_name": "Dual 4-Bit Binary Counter",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "sn74hc393.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74hc393-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "9d9536c381bec522c3541ba2743145d4d85de38109964a6e8b2acb70ec283c74",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Type": "Dual 4-bit binary counter",
      "Counters": "2 independent (4-bit each)",
      "Clock": "negative-edge triggered",
      "Reset": "active-high clear per counter",
      "Cascade": "QD to next CLK (8-bit and beyond)",
      "Logic family": "HC (high-speed CMOS)",
      "Supply voltage": "2-6 V",
      "Package": "SOIC-14"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74hc393",
    "74hc393",
    "dual binary counter",
    "4-bit counter",
    "ripple counter"
  ],
  "discovery_pitch": "SN74HC393 dual 4-bit binary ripple counter (SOIC-14) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "sn74hc393.kicad_sym",
    "sn74hc393.kicad_mod",
    "sn74hc393.glb",
    "sn74hc393.lbr",
    "docs/hero.png",
    "docs/sn74hc393-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "sn74hc393-etched.step"
  ],
  "variants": [
    {
      "mpn": "SN74HC393D (SOIC-14, tube)",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC393DR (SOIC-14, tape & reel)",
      "kind": "packaging"
    }
  ]
}