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SN74HC374DWR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC374DWR
Texas Instruments · Flip Flops · SOIC-20-300mil
SN74HC374DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low three-state output enable common to all eight Q outputs; when HIGH all outputs enter high-impedance state; when LOW outputs reflect stored flip-flop data; VI = 0 to VCC. |
| 2 | 1Q | tri_state | Three-state data output of flip-flop 1; updated on rising edge of CLK when OE is LOW; VOH min 4.4 V / VOL max 0.1 V at VCC = 4.5 V with IOH/IOL = ±6 mA; high-impedance when OE is HIGH. |
| 3 | 1D | input | Data input to flip-flop 1; logic level present at this pin is captured on the positive transition of CLK; setup time tsu = 25 ns min at VCC = 4.5 V. |
| 4 | 2D | input | Data input to flip-flop 2; logic level present at this pin is captured on the positive transition of CLK; setup time tsu = 25 ns min at VCC = 4.5 V. |
| 5 | 2Q | tri_state | Three-state data output of flip-flop 2; updated on rising edge of CLK when OE is LOW; VOH min 4.4 V / VOL max 0.1 V at VCC = 4.5 V with IOH/IOL = ±6 mA; high-impedance when OE is HIGH. |
| 6 | 3Q | tri_state | Three-state data output of flip-flop 3; updated on rising edge of CLK when OE is LOW; VOH min 4.4 V / VOL max 0.1 V at VCC = 4.5 V with IOH/IOL = ±6 mA; high-impedance when OE is HIGH. |
| 7 | 3D | input | Data input to flip-flop 3; logic level present at this pin is captured on the positive transition of CLK; setup time tsu = 25 ns min at VCC = 4.5 V. |
| 8 | 4D | input | Data input to flip-flop 4; logic level present at this pin is captured on the positive transition of CLK; setup time tsu = 25 ns min at VCC = 4.5 V. |
| 9 | 4Q | tri_state | Three-state data output of flip-flop 4; updated on rising edge of CLK when OE is LOW; VOH min 4.4 V / VOL max 0.1 V at VCC = 4.5 V with IOH/IOL = ±6 mA; high-impedance when OE is HIGH. |
| 10 | GND | power_in | Ground reference (0 V); continuous current through GND pin not to exceed ±70 mA. |
| 11 | CLK | input | Positive-edge clock common to all eight flip-flops; Q outputs update on the LOW-to-HIGH transition; fclock max 24 MHz at VCC = 4.5 V; pulse-width tw min 20 ns at VCC = 4.5 V. |
| 12 | 5Q | tri_state | Three-state data output of flip-flop 5; updated on rising edge of CLK when OE is LOW; VOH min 4.4 V / VOL max 0.1 V at VCC = 4.5 V with IOH/IOL = ±6 mA; high-impedance when OE is HIGH. |
| 13 | 5D | input | Data input to flip-flop 5; logic level present at this pin is captured on the positive transition of CLK; setup time tsu = 25 ns min at VCC = 4.5 V. |
| 14 | 6D | input | Data input to flip-flop 6; logic level present at this pin is captured on the positive transition of CLK; setup time tsu = 25 ns min at VCC = 4.5 V. |
| 15 | 6Q | tri_state | Three-state data output of flip-flop 6; updated on rising edge of CLK when OE is LOW; VOH min 4.4 V / VOL max 0.1 V at VCC = 4.5 V with IOH/IOL = ±6 mA; high-impedance when OE is HIGH. |
| 16 | 7Q | tri_state | Three-state data output of flip-flop 7; updated on rising edge of CLK when OE is LOW; VOH min 4.4 V / VOL max 0.1 V at VCC = 4.5 V with IOH/IOL = ±6 mA; high-impedance when OE is HIGH. |
| 17 | 7D | input | Data input to flip-flop 7; logic level present at this pin is captured on the positive transition of CLK; setup time tsu = 25 ns min at VCC = 4.5 V. |
| 18 | 8D | input | Data input to flip-flop 8; logic level present at this pin is captured on the positive transition of CLK; setup time tsu = 25 ns min at VCC = 4.5 V. |
| 19 | 8Q | tri_state | Three-state data output of flip-flop 8; updated on rising edge of CLK when OE is LOW; VOH min 4.4 V / VOL max 0.1 V at VCC = 4.5 V with IOH/IOL = ±6 mA; high-impedance when OE is HIGH. |
| 20 | VCC | power_in | Positive supply voltage; recommended operating range 2 V to 6 V; ICC max 80 µA at VCC = 6 V, IO = 0; bypass with 0.1 µF capacitor as close to pin as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74HC374DWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
sn74hc374dwr-etched.step/sn74hc374dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc374dwr.step/sn74hc374dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
e72f5f2d1a24107d, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-4-6(text+vision), consensusclaude-opus-4-7(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).