component
SN74HC373N
Public Made by Adomby adom
lingxingic Latches, DIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC373N
lingxingic · Latches · DIP-20
SN74HC373N from lingxingic, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low common three-state output enable; a high level puts outputs Q0-Q7 in high impedance and does not change the latch contents. |
| 2 | Q0 | tri_state | Non-inverting three-state latch output for bit 0, high impedance when OE is high. |
| 3 | D0 | input | Data input for bit 0; with LE high the latch is transparent, and the input has clamp diodes so it can be driven above VCC through a current-limiting resistor. |
| 4 | D1 | input | Data input for bit 1; with LE high the latch is transparent, and the input has clamp diodes so it can be driven above VCC through a current-limiting resistor. |
| 5 | Q1 | tri_state | Non-inverting three-state latch output for bit 1, high impedance when OE is high. |
| 6 | Q2 | tri_state | Non-inverting three-state latch output for bit 2, high impedance when OE is high. |
| 7 | D2 | input | Data input for bit 2; with LE high the latch is transparent, and the input has clamp diodes so it can be driven above VCC through a current-limiting resistor. |
| 8 | D3 | input | Data input for bit 3; with LE high the latch is transparent, and the input has clamp diodes so it can be driven above VCC through a current-limiting resistor. |
| 9 | Q3 | tri_state | Non-inverting three-state latch output for bit 3, high impedance when OE is high. |
| 10 | GND | power_in | Ground reference (0 V). |
| 11 | LE | input | Latch enable input, active high; while high the latch is transparent, and it stores the data present before the falling edge of LE. |
| 12 | Q4 | tri_state | Non-inverting three-state latch output for bit 4, high impedance when OE is high. |
| 13 | D4 | input | Data input for bit 4; with LE high the latch is transparent, and the input has clamp diodes so it can be driven above VCC through a current-limiting resistor. |
| 14 | D5 | input | Data input for bit 5; with LE high the latch is transparent, and the input has clamp diodes so it can be driven above VCC through a current-limiting resistor. |
| 15 | Q5 | tri_state | Non-inverting three-state latch output for bit 5, high impedance when OE is high. |
| 16 | Q6 | tri_state | Non-inverting three-state latch output for bit 6, high impedance when OE is high. |
| 17 | D6 | input | Data input for bit 6; with LE high the latch is transparent, and the input has clamp diodes so it can be driven above VCC through a current-limiting resistor. |
| 18 | D7 | input | Data input for bit 7; with LE high the latch is transparent, and the input has clamp diodes so it can be driven above VCC through a current-limiting resistor. |
| 19 | Q7 | tri_state | Non-inverting three-state latch output for bit 7, high impedance when OE is high. |
| 20 | VCC | power_in | Power supply: SN74HC373 is specified at 2.0-6.0 V and SN74HCT373 at 4.5-5.5 V, with an absolute maximum of 7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | DIP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 7 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V或VI>VCC+0.5V | 7 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V或VO>VCC+0.5V | 7 | |
| Output current | IO | -35 | 35 | mA | VO=-0.5V～(VCC+0.5V) | 7 | |
| Supply current | ICC | 70 | mA | 7 | |||
| Ground current | IGND | -70 | mA | 7 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 7 | ||
| Total power dissipation | Ptot | 500 | mW | 7 | |||
| Soldering temperature (DIP) | TL | 245 | ℃ | 10 s; DIP package | 7 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | SN74HC373 | 7 |
| Input voltage | VI | 0 | V | max printed as VCC | 7 | ||
| Output voltage | VO | 0 | V | max printed as VCC | 7 | ||
| Input rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 7 | ||
| Input rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 7 | |
| Input rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 7 | ||
| Operating ambient temperature | Tamb | -40 | 125 | ℃ | 7 | ||
| High-level input voltage | VIH | 1.5 | 1.2 | V | VCC=2.0V | 8 | |
| High-level input voltage | VIH | 3.15 | 2.4 | V | VCC=4.5V | 8 | |
| High-level input voltage | VIH | 4.2 | 3.2 | V | VCC=6.0V | 8 | |
| Low-level input voltage | VIL | 0.8 | 0.5 | V | VCC=2.0V | 8 | |
| Low-level input voltage | VIL | 2.1 | 1.35 | V | VCC=4.5V | 8 | |
| Low-level input voltage | VIL | 2.8 | 1.8 | V | VCC=6.0V | 8 | |
| High-level output voltage | VOH | 1.9 | 2 | V | VI=VIH或VIL; IO=-20uA; VCC=2.0V | 8 | |
| High-level output voltage | VOH | 4.4 | 4.5 | V | VI=VIH或VIL; IO=-20uA; VCC=4.5V | 8 | |
| High-level output voltage | VOH | 5.9 | 6 | V | VI=VIH或VIL; IO=-20uA; VCC=6.0V | 8 | |
| High-level output voltage | VOH | 3.98 | 4.32 | V | VI=VIH或VIL; IO=-6.0mA; VCC=4.5V | 8 | |
| High-level output voltage | VOH | 5.48 | 5.81 | V | VI=VIH或VIL; IO=-7.8mA; VCC=6.0V | 8 | |
| Low-level output voltage | VOL | 0 | 0.1 | V | VI=VIH或VIL; IO=20uA; VCC=2.0V | 8 | |
| Low-level output voltage | VOL | 0.15 | 0.26 | V | VI=VIH或VIL; IO=6.0mA; VCC=4.5V | 8 | |
| Low-level output voltage | VOL | 0.16 | 0.26 | V | VI=VIH或VIL; IO=7.8mA; VCC=6.0V | 8 | |
| Input leakage current | II | -1 | 1 | uA | VI=VCC或GND; VCC=6.0V | 8 | |
| Off-state output current | IOZ | -1 | 1 | uA | VI=VIH或VIL; VCC=6.0V; VO=VCC or GND | 8 | |
| Quiescent supply current | ICC | 8 | uA | VI=VCC或GND; IO=0A; VCC=6.0V | 8 | ||
| Propagation delay Dn to Qn | tpd | 41 | 150 | ns | VCC=2.0V; CL=50pF; see Fig.7 | 11 | |
| Propagation delay Dn to Qn | tpd | 15 | 30 | ns | VCC=4.5V; CL=50pF; see Fig.7 | 11 | |
| Propagation delay Dn to Qn | tpd | 12 | 26 | ns | VCC=6.0V; CL=50pF; see Fig.7 | 11 | |
| Propagation delay LE to Qn | tpd | 50 | 175 | ns | VCC=2.0V; CL=50pF; see Fig.8 | 11 | |
| Propagation delay LE to Qn | tpd | 18 | 35 | ns | VCC=4.5V; CL=50pF; see Fig.8 | 11 | |
| Propagation delay LE to Qn | tpd | 14 | 30 | ns | VCC=6.0V; CL=50pF; see Fig.8 | 11 | |
| Output enable time OE to Qn | ten | 44 | 150 | ns | VCC=2.0V; CL=50pF; see Fig.9 | 11 | |
| Output enable time OE to Qn | ten | 16 | 30 | ns | VCC=4.5V; CL=50pF; see Fig.9 | 11 | |
| Output enable time OE to Qn | ten | 13 | 26 | ns | VCC=6.0V; CL=50pF; see Fig.9 | 11 | |
| Output disable time OE to Qn | tdis | 47 | 150 | ns | VCC=2.0V; CL=50pF; see Fig.9 | 11 | |
| Output disable time OE to Qn | tdis | 17 | 30 | ns | VCC=4.5V; CL=50pF; see Fig.9 | 11 | |
| Output disable time OE to Qn | tdis | 14 | 26 | ns | VCC=6.0V; CL=50pF; see Fig.9 | 11 | |
| Output transition time Qn | tt | 14 | 60 | ns | VCC=2.0V; CL=50pF; see Fig.7,8 | 11 | |
| Output transition time Qn | tt | 5 | 12 | ns | VCC=4.5V; CL=50pF; see Fig.7,8 | 11 | |
| Output transition time Qn | tt | 4 | 10 | ns | VCC=6.0V; CL=50pF; see Fig.7,8 | 11 | |
| LE high pulse width | tW | 80 | 17 | ns | VCC=2.0V; LE high; see Fig.8 | 11 | |
| LE high pulse width | tW | 16 | 6 | ns | VCC=4.5V; LE high; see Fig.8 | 11 | |
| LE high pulse width | tW | 14 | 5 | ns | VCC=6.0V; LE high; see Fig.8 | 11 | |
| Setup time Dn to LE | tsu | 50 | 14 | ns | VCC=2.0V; see Fig.10 | 11 | |
| Setup time Dn to LE | tsu | 10 | 5 | ns | VCC=4.5V; see Fig.10 | 11 | |
| Setup time Dn to LE | tsu | 9 | 4 | ns | VCC=6.0V; see Fig.10 | 11 | |
| Hold time Dn to LE | th | 5 | -8 | ns | VCC=2.0V; see Fig.10 | 11 | |
| Hold time Dn to LE | th | 5 | -3 | ns | VCC=4.5V; see Fig.10 | 11 | |
| Hold time Dn to LE | th | 5 | -2 | ns | VCC=6.0V; see Fig.10 | 11 |
CAD (KiCad official)
- Symbol:
SN74HC373N - Footprint:
Package_DIP:DIP-20_W7.62mm - 3D model: DIP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74hc373n-etched.step/sn74hc373n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc373n.step/sn74hc373n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (22 pp, sha256
0f3c8499ba7a7a92, retrieved 2026-10-15, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).