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SN74HC373DTR

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by adom

XBLW Latches, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HC373DTR

XBLW · Latches · SOP-20

SN74HC373DTR from XBLW, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input 3-state output enable input, active LOW; HIGH forces all Q outputs to high-impedance state.
2 Q0 tri_state 3-state latch output for bit 0; reflects D0 when LE is HIGH, holds last state when LE goes LOW, high-Z when OE is HIGH.
3 D0 input Data input for latch 0; inputs include clamp diodes to interface voltages in excess of VCC.
4 D1 input Data input for latch 1; inputs include clamp diodes to interface voltages in excess of VCC.
5 Q1 tri_state 3-state latch output for bit 1; reflects D1 when LE is HIGH, holds last state when LE goes LOW, high-Z when OE is HIGH.
6 Q2 tri_state 3-state latch output for bit 2; reflects D2 when LE is HIGH, holds last state when LE goes LOW, high-Z when OE is HIGH.
7 D2 input Data input for latch 2; inputs include clamp diodes to interface voltages in excess of VCC.
8 D3 input Data input for latch 3; inputs include clamp diodes to interface voltages in excess of VCC.
9 Q3 tri_state 3-state latch output for bit 3; reflects D3 when LE is HIGH, holds last state when LE goes LOW, high-Z when OE is HIGH.
10 GND power_in Ground reference, 0 V.
11 LE input Latch enable input, active HIGH; while HIGH the latches are transparent; a HIGH-to-LOW transition stores the data present at the D inputs.
12 Q4 tri_state 3-state latch output for bit 4; reflects D4 when LE is HIGH, holds last state when LE goes LOW, high-Z when OE is HIGH.
13 D4 input Data input for latch 4; inputs include clamp diodes to interface voltages in excess of VCC.
14 D5 input Data input for latch 5; inputs include clamp diodes to interface voltages in excess of VCC.
15 Q5 tri_state 3-state latch output for bit 5; reflects D5 when LE is HIGH, holds last state when LE goes LOW, high-Z when OE is HIGH.
16 Q6 tri_state 3-state latch output for bit 6; reflects D6 when LE is HIGH, holds last state when LE goes LOW, high-Z when OE is HIGH.
17 D6 input Data input for latch 6; inputs include clamp diodes to interface voltages in excess of VCC.
18 D7 input Data input for latch 7; inputs include clamp diodes to interface voltages in excess of VCC.
19 Q7 tri_state 3-state latch output for bit 7; reflects D7 when LE is HIGH, holds last state when LE goes LOW, high-Z when OE is HIGH.
20 VCC power_in Positive supply voltage; recommended operating range 2.0 V to 6.0 V, absolute maximum +7.0 V.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HC373DTR
  • Footprint: Package_SO:SOP-20_7.5x12.8mm_P1.27mm
  • 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: sn74hc373dtr-etched.step / sn74hc373dtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc373dtr.step / sn74hc373dtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (20 pp, sha256 db32ab70148c9cf4, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF