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SN74HC373DBR

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Texas Instruments Latches, SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HC373DBR

Texas Instruments · Latches · SSOP-20-208mil

SN74HC373DBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable: when low the eight Q outputs are enabled, and when high they are forced to the high-impedance state without affecting the latches.
2 1Q tri_state Latch 1 three-state true output, able to drive up to 15 LSTTL loads and high-impedance when OE is high.
3 1D input Data input of latch 1; Q follows D while LE is high and holds the level present at D when LE goes low.
4 2D input Data input of latch 2; Q follows D while LE is high and holds the level present at D when LE goes low.
5 2Q tri_state Latch 2 three-state true output, able to drive up to 15 LSTTL loads and high-impedance when OE is high.
6 3Q tri_state Latch 3 three-state true output, able to drive up to 15 LSTTL loads and high-impedance when OE is high.
7 3D input Data input of latch 3; Q follows D while LE is high and holds the level present at D when LE goes low.
8 4D input Data input of latch 4; Q follows D while LE is high and holds the level present at D when LE goes low.
9 4Q tri_state Latch 4 three-state true output, able to drive up to 15 LSTTL loads and high-impedance when OE is high.
10 GND power_in Ground reference for the device.
11 LE input Latch enable: while high the Q outputs follow the D inputs, and the Q outputs are latched at the D levels when LE goes low.
12 5Q tri_state Latch 5 three-state true output, able to drive up to 15 LSTTL loads and high-impedance when OE is high.
13 5D input Data input of latch 5; Q follows D while LE is high and holds the level present at D when LE goes low.
14 6D input Data input of latch 6; Q follows D while LE is high and holds the level present at D when LE goes low.
15 6Q tri_state Latch 6 three-state true output, able to drive up to 15 LSTTL loads and high-impedance when OE is high.
16 7Q tri_state Latch 7 three-state true output, able to drive up to 15 LSTTL loads and high-impedance when OE is high.
17 7D input Data input of latch 7; Q follows D while LE is high and holds the level present at D when LE goes low.
18 8D input Data input of latch 8; Q follows D while LE is high and holds the level present at D when LE goes low.
19 8Q tri_state Latch 8 three-state true output, able to drive up to 15 LSTTL loads and high-impedance when OE is high.
20 VCC power_in Supply voltage; recommended 2 V to 6 V (absolute maximum -0.5 V to 7 V), with a 0.1 µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20-208mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage (recommended) VCC 2 5 6 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Input transition rise and fall time Δt/Δv 1000 ns VCC = 2 V 4
Input transition rise and fall time Δt/Δv 500 ns VCC = 4.5 V 4
Input transition rise and fall time Δt/Δv 400 ns VCC = 6 V 4
Operating free-air temperature TA -40 85 °C SN74HC373 4
High-level output voltage VOH 1.9 1.998 V VI = VIH or VIL, IOH = -20 µA, VCC = 2 V 5
High-level output voltage VOH 4.4 4.499 V VI = VIH or VIL, IOH = -20 µA, VCC = 4.5 V 5
High-level output voltage VOH 5.9 5.999 V VI = VIH or VIL, IOH = -20 µA, VCC = 6 V 5
High-level output voltage VOH 3.84 4.3 V VI = VIH or VIL, IOH = -6 mA, VCC = 4.5 V 5
High-level output voltage VOH 5.34 5.8 V VI = VIH or VIL, IOH = -7.8 mA, VCC = 6 V 5
Low-level output voltage VOL 0.002 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC = 2 V 5
Low-level output voltage VOL 0.001 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC = 4.5 V 5
Low-level output voltage VOL 0.17 0.33 V VI = VIH or VIL, IOL = 6 mA, VCC = 4.5 V 5
Low-level output voltage VOL 0.15 0.33 V VI = VIH or VIL, IOL = 7.8 mA, VCC = 6 V 5
Input leakage current II -1000 0.1 1000 nA VI = VCC or 0, VCC = 6 V 5
Off-state (high-impedance) output current IOZ -5 0.01 5 µA VO = VCC or 0, VCC = 6 V 5
Supply current ICC 80 µA VI = VCC or 0, IO = 0, VCC = 6 V 5
Input capacitance Ci 3 10 pF VCC = 2 V to 6 V 5
Pulse duration, LE high tw 100 ns VCC = 2 V 5
Pulse duration, LE high tw 20 ns VCC = 4.5 V 5
Pulse duration, LE high tw 17 ns VCC = 6 V 5
Setup time, data before LE↓ tsu 63 ns VCC = 2 V 5
Setup time, data before LE↓ tsu 13 ns VCC = 4.5 V 5
Setup time, data before LE↓ tsu 11 ns VCC = 6 V 5
Hold time, data after LE↓ th 24 ns VCC = 2 V 5
Hold time, data after LE↓ th 12 ns VCC = 4.5 V 5
Propagation delay, D to Q tpd 13 32 ns VCC = 6 V, CL = 50 pF 6
Propagation delay, LE to Q tpd 15 38 ns VCC = 6 V, CL = 50 pF 6
Enable time, OE to Q ten 14 32 ns VCC = 6 V, CL = 50 pF 6
Disable time, OE to Q tdis 13 32 ns VCC = 6 V, CL = 50 pF 6
Output transition time tt 6 13 ns VCC = 6 V, CL = 50 pF 6
Propagation delay, D to Q tpd 19 43 ns VCC = 6 V, CL = 150 pF 6
Propagation delay, LE to Q tpd 20 48 ns VCC = 6 V, CL = 150 pF 6
Enable time, OE to Q ten 19 43 ns VCC = 6 V, CL = 150 pF 6
Output transition time tt 13 45 ns VCC = 6 V, CL = 150 pF 6
Junction-to-ambient thermal resistance (DB, SSOP) RθJA 122.7 °C/W 4
Junction-to-case (top) thermal resistance (DB, SSOP) RθJC(top) 81.6 °C/W 4
Junction-to-board thermal resistance (DB, SSOP) RθJB 77.5 °C/W 4
Junction-to-top characterization parameter (DB, SSOP) ΨJT 46.1 °C/W 4
Junction-to-board characterization parameter (DB, SSOP) ΨJB 77.1 °C/W 4

CAD (KiCad official)

  • Symbol: SN74HC373DBR
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74hc373dbr-etched.step / sn74hc373dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc373dbr.step / sn74hc373dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 21a57e66e15622b1, retrieved 2026-10-18, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF