component
SN74HC373D
Public Made by Adomby adom
lingxingic Latches, SOP-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74HC373D
lingxingic · Latches · SOP-20-300mil
SN74HC373D from lingxingic, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Three-state output enable input, active low; a high level puts the Q outputs in high impedance and does not affect the latch state. |
| 2 | Q0 | tri_state | Three-state latch output 0; high impedance when OE is high. |
| 3 | D0 | input | Data input 0; transparent to the output while LE is high and latched on the LE falling edge. |
| 4 | D1 | input | Data input 1; transparent to the output while LE is high and latched on the LE falling edge. |
| 5 | Q1 | tri_state | Three-state latch output 1; high impedance when OE is high. |
| 6 | Q2 | tri_state | Three-state latch output 2; high impedance when OE is high. |
| 7 | D2 | input | Data input 2; transparent to the output while LE is high and latched on the LE falling edge. |
| 8 | D3 | input | Data input 3; transparent to the output while LE is high and latched on the LE falling edge. |
| 9 | Q3 | tri_state | Three-state latch output 3; high impedance when OE is high. |
| 10 | GND | power_in | Ground (0 V). |
| 11 | LE | input | Latch enable input, active high; when high data passes through the latch, and when low the latch holds the data present before the LE falling edge. |
| 12 | Q4 | tri_state | Three-state latch output 4; high impedance when OE is high. |
| 13 | D4 | input | Data input 4; transparent to the output while LE is high and latched on the LE falling edge. |
| 14 | D5 | input | Data input 5; transparent to the output while LE is high and latched on the LE falling edge. |
| 15 | Q5 | tri_state | Three-state latch output 5; high impedance when OE is high. |
| 16 | Q6 | tri_state | Three-state latch output 6; high impedance when OE is high. |
| 17 | D6 | input | Data input 6; transparent to the output while LE is high and latched on the LE falling edge. |
| 18 | D7 | input | Data input 7; transparent to the output while LE is high and latched on the LE falling edge. |
| 19 | Q7 | tri_state | Three-state latch output 7; high impedance when OE is high. |
| 20 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for SN74HC373 and 4.5 V to 5.5 V for SN74HCT373. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 (Supply voltage) | VCC | -0.5 | 7 | V | 7 | ||
| 输入钳位电流 (Input clamp current) | IIK | -20 | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 7 | |
| 输出钳位电流 (Output clamp current) | IOK | -20 | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 7 | |
| 输出电流 (Output current) | IO | -35 | 35 | mA | VO=-0.5V～(VCC+0.5V) | 7 | |
| 电源电流 (Supply current) | ICC | 70 | mA | 7 | |||
| 地电流 (Ground current) | IGND | -70 | mA | 7 | |||
| 贮存温度 (Storage temperature) | Tstg | -65 | 150 | ℃ | 7 | ||
| 总功耗 (Total power dissipation) | Ptot | 500 | mW | 7 | |||
| 焊接温度 (Soldering temperature) | TL | 260 | ℃ | 10 秒；SOP/TSSOP/SOP(M) | 7 | ||
| 电源电压 (Supply voltage, HC) | VCC | 2 | 5 | 6 | V | SN74HC373 | 7 |
| 输入电压 (Input voltage) | VI | 0 | V | SN74HC373; 最大值印刷为 VCC | 7 | ||
| 输出电压 (Output voltage) | VO | 0 | V | SN74HC373; 最大值印刷为 VCC | 7 | ||
| 输入上升和下降转换速率 (Input rise and fall rate) | Δt/ΔV | 625 | ns/V | VCC=2.0V | 7 | ||
| 输入上升和下降转换速率 (Input rise and fall rate) | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 7 | |
| 输入上升和下降转换速率 (Input rise and fall rate) | Δt/ΔV | 83 | ns/V | VCC=6.0V | 7 | ||
| 工作环境温度 (Operating ambient temperature) | Tamb | -40 | 125 | ℃ | 7 | ||
| 高电平输入电压 (High-level input voltage) | VIH | 1.5 | 1.2 | V | VCC=2.0V | 8 | |
| 高电平输入电压 (High-level input voltage) | VIH | 3.15 | 2.4 | V | VCC=4.5V | 8 | |
| 高电平输入电压 (High-level input voltage) | VIH | 4.2 | 3.2 | V | VCC=6.0V | 8 | |
| 低电平输入电压 (Low-level input voltage) | VIL | 0.8 | 0.5 | V | VCC=2.0V | 8 | |
| 低电平输入电压 (Low-level input voltage) | VIL | 2.1 | 1.35 | V | VCC=4.5V | 8 | |
| 低电平输入电压 (Low-level input voltage) | VIL | 2.8 | 1.8 | V | VCC=6.0V | 8 | |
| 高电平输出电压 (High-level output voltage) | VOH | 1.9 | 2 | V | VI=VIH或VIL；IO=-20uA；VCC=2.0V | 8 | |
| 高电平输出电压 (High-level output voltage) | VOH | 4.4 | 4.5 | V | VI=VIH或VIL；IO=-20uA；VCC=4.5V | 8 | |
| 高电平输出电压 (High-level output voltage) | VOH | 5.9 | 6 | V | VI=VIH或VIL；IO=-20uA；VCC=6.0V | 8 | |
| 高电平输出电压 (High-level output voltage) | VOH | 3.98 | 4.32 | V | VI=VIH或VIL；IO=-6.0mA；VCC=4.5V | 8 | |
| 高电平输出电压 (High-level output voltage) | VOH | 5.48 | 5.81 | V | VI=VIH或VIL；IO=-7.8mA；VCC=6.0V | 8 | |
| 低电平输出电压 (Low-level output voltage) | VOL | 0 | 0.1 | V | VI=VIH或VIL；IO=20uA；VCC=2.0V | 8 | |
| 低电平输出电压 (Low-level output voltage) | VOL | 0.15 | 0.26 | V | VI=VIH或VIL；IO=6.0mA；VCC=4.5V | 8 | |
| 低电平输出电压 (Low-level output voltage) | VOL | 0.16 | 0.26 | V | VI=VIH或VIL；IO=7.8mA；VCC=6.0V | 8 | |
| 输入漏电流 (Input leakage current) | II | -1 | 1 | uA | VI=VCC或GND；VCC=6.0V | 8 | |
| 截止状态输出电流 (Off-state output current) | IOZ | -1 | 1 | uA | VI=VIH或VIL；VCC=6.0V；VO=VCC or GND | 8 | |
| 静态电流 (Quiescent supply current) | ICC | 8 | uA | VI=VCC或GND；IO=0A；VCC=6.0V | 8 | ||
| 传输延时 Dn到Qn (Propagation delay) | tpd | 41 | 150 | ns | Dn到Qn；见图7；VCC=2.0V；CL=50pF | 11 | |
| 传输延时 Dn到Qn (Propagation delay) | tpd | 15 | 30 | ns | Dn到Qn；见图7；VCC=4.5V；CL=50pF | 11 | |
| 传输延时 Dn到Qn (Propagation delay) | tpd | 12 | 26 | ns | Dn到Qn；见图7；VCC=6.0V；CL=50pF | 11 | |
| 传输延时 LE到Qn (Propagation delay) | tpd | 50 | 175 | ns | LE到Qn；见图8；VCC=2.0V；CL=50pF | 11 | |
| 传输延时 LE到Qn (Propagation delay) | tpd | 18 | 35 | ns | LE到Qn；见图8；VCC=4.5V；CL=50pF | 11 | |
| 传输延时 LE到Qn (Propagation delay) | tpd | 14 | 30 | ns | LE到Qn；见图8；VCC=6.0V；CL=50pF | 11 | |
| 使能时间 OE到Qn (Output enable time) | ten | 44 | 150 | ns | 见图9；VCC=2.0V；CL=50pF | 11 | |
| 使能时间 OE到Qn (Output enable time) | ten | 16 | 30 | ns | 见图9；VCC=4.5V；CL=50pF | 11 | |
| 使能时间 OE到Qn (Output enable time) | ten | 13 | 26 | ns | 见图9；VCC=6.0V；CL=50pF | 11 | |
| 失能时间 OE到Qn (Output disable time) | tdis | 47 | 150 | ns | 见图9；VCC=2.0V；CL=50pF | 11 | |
| 失能时间 OE到Qn (Output disable time) | tdis | 17 | 30 | ns | 见图9；VCC=4.5V；CL=50pF | 11 | |
| 失能时间 OE到Qn (Output disable time) | tdis | 14 | 26 | ns | 见图9；VCC=6.0V；CL=50pF | 11 | |
| 转换时间 (Output transition time) | tt | 14 | 60 | ns | Qn；见图7，8；VCC=2.0V；CL=50pF | 11 | |
| 转换时间 (Output transition time) | tt | 5 | 12 | ns | Qn；见图7，8；VCC=4.5V；CL=50pF | 11 | |
| 转换时间 (Output transition time) | tt | 4 | 10 | ns | Qn；见图7，8；VCC=6.0V；CL=50pF | 11 | |
| 脉冲宽度 LE高电平 (Pulse width) | tW | 80 | 17 | ns | LE为高电平；见图8；VCC=2.0V；CL=50pF | 11 | |
| 脉冲宽度 LE高电平 (Pulse width) | tW | 16 | 6 | ns | LE为高电平；见图8；VCC=4.5V；CL=50pF | 11 | |
| 脉冲宽度 LE高电平 (Pulse width) | tW | 14 | 5 | ns | LE为高电平；见图8；VCC=6.0V；CL=50pF | 11 | |
| 建立时间 Dn到LE (Setup time) | tsu | 50 | 14 | ns | Dn到LE；见图10；VCC=2.0V；CL=50pF | 11 | |
| 建立时间 Dn到LE (Setup time) | tsu | 10 | 5 | ns | Dn到LE；见图10；VCC=4.5V；CL=50pF | 11 | |
| 建立时间 Dn到LE (Setup time) | tsu | 9 | 4 | ns | Dn到LE；见图10；VCC=6.0V；CL=50pF | 11 | |
| 保持时间 Dn到LE (Hold time) | th | 5 | -8 | ns | Dn到LE；见图10；VCC=2.0V；CL=50pF | 11 | |
| 保持时间 Dn到LE (Hold time) | th | 5 | -3 | ns | Dn到LE；见图10；VCC=4.5V；CL=50pF | 11 | |
| 保持时间 Dn到LE (Hold time) | th | 5 | -2 | ns | Dn到LE；见图10；VCC=6.0V；CL=50pF | 11 |
CAD (KiCad official)
- Symbol:
SN74HC373D - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
sn74hc373d-etched.step/sn74hc373d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc373d.step/sn74hc373d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (22 pp, sha256
0f3c8499ba7a7a92, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HC373D
**lingxingic** · Latches · SOP-20-300mil
SN74HC373D from lingxingic, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Three-state output enable input, active low; a high level puts the Q outputs in high impedance and does not affect the latch state. |
| 2 | Q0 | tri_state | Three-state latch output 0; high impedance when OE is high. |
| 3 | D0 | input | Data input 0; transparent to the output while LE is high and latched on the LE falling edge. |
| 4 | D1 | input | Data input 1; transparent to the output while LE is high and latched on the LE falling edge. |
| 5 | Q1 | tri_state | Three-state latch output 1; high impedance when OE is high. |
| 6 | Q2 | tri_state | Three-state latch output 2; high impedance when OE is high. |
| 7 | D2 | input | Data input 2; transparent to the output while LE is high and latched on the LE falling edge. |
| 8 | D3 | input | Data input 3; transparent to the output while LE is high and latched on the LE falling edge. |
| 9 | Q3 | tri_state | Three-state latch output 3; high impedance when OE is high. |
| 10 | GND | power_in | Ground (0 V). |
| 11 | LE | input | Latch enable input, active high; when high data passes through the latch, and when low the latch holds the data present before the LE falling edge. |
| 12 | Q4 | tri_state | Three-state latch output 4; high impedance when OE is high. |
| 13 | D4 | input | Data input 4; transparent to the output while LE is high and latched on the LE falling edge. |
| 14 | D5 | input | Data input 5; transparent to the output while LE is high and latched on the LE falling edge. |
| 15 | Q5 | tri_state | Three-state latch output 5; high impedance when OE is high. |
| 16 | Q6 | tri_state | Three-state latch output 6; high impedance when OE is high. |
| 17 | D6 | input | Data input 6; transparent to the output while LE is high and latched on the LE falling edge. |
| 18 | D7 | input | Data input 7; transparent to the output while LE is high and latched on the LE falling edge. |
| 19 | Q7 | tri_state | Three-state latch output 7; high impedance when OE is high. |
| 20 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for SN74HC373 and 4.5 V to 5.5 V for SN74HCT373. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 (Supply voltage) | VCC | -0.5 | | 7 | V | | 7 |
| 输入钳位电流 (Input clamp current) | IIK | -20 | | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 7 |
| 输出钳位电流 (Output clamp current) | IOK | -20 | | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 7 |
| 输出电流 (Output current) | IO | -35 | | 35 | mA | VO=-0.5V～(VCC+0.5V) | 7 |
| 电源电流 (Supply current) | ICC | | | 70 | mA | | 7 |
| 地电流 (Ground current) | IGND | -70 | | | mA | | 7 |
| 贮存温度 (Storage temperature) | Tstg | -65 | | 150 | ℃ | | 7 |
| 总功耗 (Total power dissipation) | Ptot | | | 500 | mW | | 7 |
| 焊接温度 (Soldering temperature) | TL | | | 260 | ℃ | 10 秒；SOP/TSSOP/SOP(M) | 7 |
| 电源电压 (Supply voltage, HC) | VCC | 2 | 5 | 6 | V | SN74HC373 | 7 |
| 输入电压 (Input voltage) | VI | 0 | | | V | SN74HC373; 最大值印刷为 VCC | 7 |
| 输出电压 (Output voltage) | VO | 0 | | | V | SN74HC373; 最大值印刷为 VCC | 7 |
| 输入上升和下降转换速率 (Input rise and fall rate) | Δt/ΔV | | | 625 | ns/V | VCC=2.0V | 7 |
| 输入上升和下降转换速率 (Input rise and fall rate) | Δt/ΔV | | 1.67 | 139 | ns/V | VCC=4.5V | 7 |
| 输入上升和下降转换速率 (Input rise and fall rate) | Δt/ΔV | | | 83 | ns/V | VCC=6.0V | 7 |
| 工作环境温度 (Operating ambient temperature) | Tamb | -40 | | 125 | ℃ | | 7 |
| 高电平输入电压 (High-level input voltage) | VIH | 1.5 | 1.2 | | V | VCC=2.0V | 8 |
| 高电平输入电压 (High-level input voltage) | VIH | 3.15 | 2.4 | | V | VCC=4.5V | 8 |
| 高电平输入电压 (High-level input voltage) | VIH | 4.2 | 3.2 | | V | VCC=6.0V | 8 |
| 低电平输入电压 (Low-level input voltage) | VIL | | 0.8 | 0.5 | V | VCC=2.0V | 8 |
| 低电平输入电压 (Low-level input voltage) | VIL | | 2.1 | 1.35 | V | VCC=4.5V | 8 |
| 低电平输入电压 (Low-level input voltage) | VIL | | 2.8 | 1.8 | V | VCC=6.0V | 8 |
| 高电平输出电压 (High-level output voltage) | VOH | 1.9 | 2 | | V | VI=VIH或VIL；IO=-20uA；VCC=2.0V | 8 |
| 高电平输出电压 (High-level output voltage) | VOH | 4.4 | 4.5 | | V | VI=VIH或VIL；IO=-20uA；VCC=4.5V | 8 |
| 高电平输出电压 (High-level output voltage) | VOH | 5.9 | 6 | | V | VI=VIH或VIL；IO=-20uA；VCC=6.0V | 8 |
| 高电平输出电压 (High-level output voltage) | VOH | 3.98 | 4.32 | | V | VI=VIH或VIL；IO=-6.0mA；VCC=4.5V | 8 |
| 高电平输出电压 (High-level output voltage) | VOH | 5.48 | 5.81 | | V | VI=VIH或VIL；IO=-7.8mA；VCC=6.0V | 8 |
| 低电平输出电压 (Low-level output voltage) | VOL | | 0 | 0.1 | V | VI=VIH或VIL；IO=20uA；VCC=2.0V | 8 |
| 低电平输出电压 (Low-level output voltage) | VOL | | 0.15 | 0.26 | V | VI=VIH或VIL；IO=6.0mA；VCC=4.5V | 8 |
| 低电平输出电压 (Low-level output voltage) | VOL | | 0.16 | 0.26 | V | VI=VIH或VIL；IO=7.8mA；VCC=6.0V | 8 |
| 输入漏电流 (Input leakage current) | II | -1 | | 1 | uA | VI=VCC或GND；VCC=6.0V | 8 |
| 截止状态输出电流 (Off-state output current) | IOZ | -1 | | 1 | uA | VI=VIH或VIL；VCC=6.0V；VO=VCC or GND | 8 |
| 静态电流 (Quiescent supply current) | ICC | | | 8 | uA | VI=VCC或GND；IO=0A；VCC=6.0V | 8 |
| 传输延时 Dn到Qn (Propagation delay) | tpd | | 41 | 150 | ns | Dn到Qn；见图7；VCC=2.0V；CL=50pF | 11 |
| 传输延时 Dn到Qn (Propagation delay) | tpd | | 15 | 30 | ns | Dn到Qn；见图7；VCC=4.5V；CL=50pF | 11 |
| 传输延时 Dn到Qn (Propagation delay) | tpd | | 12 | 26 | ns | Dn到Qn；见图7；VCC=6.0V；CL=50pF | 11 |
| 传输延时 LE到Qn (Propagation delay) | tpd | | 50 | 175 | ns | LE到Qn；见图8；VCC=2.0V；CL=50pF | 11 |
| 传输延时 LE到Qn (Propagation delay) | tpd | | 18 | 35 | ns | LE到Qn；见图8；VCC=4.5V；CL=50pF | 11 |
| 传输延时 LE到Qn (Propagation delay) | tpd | | 14 | 30 | ns | LE到Qn；见图8；VCC=6.0V；CL=50pF | 11 |
| 使能时间 OE到Qn (Output enable time) | ten | | 44 | 150 | ns | 见图9；VCC=2.0V；CL=50pF | 11 |
| 使能时间 OE到Qn (Output enable time) | ten | | 16 | 30 | ns | 见图9；VCC=4.5V；CL=50pF | 11 |
| 使能时间 OE到Qn (Output enable time) | ten | | 13 | 26 | ns | 见图9；VCC=6.0V；CL=50pF | 11 |
| 失能时间 OE到Qn (Output disable time) | tdis | | 47 | 150 | ns | 见图9；VCC=2.0V；CL=50pF | 11 |
| 失能时间 OE到Qn (Output disable time) | tdis | | 17 | 30 | ns | 见图9；VCC=4.5V；CL=50pF | 11 |
| 失能时间 OE到Qn (Output disable time) | tdis | | 14 | 26 | ns | 见图9；VCC=6.0V；CL=50pF | 11 |
| 转换时间 (Output transition time) | tt | | 14 | 60 | ns | Qn；见图7，8；VCC=2.0V；CL=50pF | 11 |
| 转换时间 (Output transition time) | tt | | 5 | 12 | ns | Qn；见图7，8；VCC=4.5V；CL=50pF | 11 |
| 转换时间 (Output transition time) | tt | | 4 | 10 | ns | Qn；见图7，8；VCC=6.0V；CL=50pF | 11 |
| 脉冲宽度 LE高电平 (Pulse width) | tW | 80 | 17 | | ns | LE为高电平；见图8；VCC=2.0V；CL=50pF | 11 |
| 脉冲宽度 LE高电平 (Pulse width) | tW | 16 | 6 | | ns | LE为高电平；见图8；VCC=4.5V；CL=50pF | 11 |
| 脉冲宽度 LE高电平 (Pulse width) | tW | 14 | 5 | | ns | LE为高电平；见图8；VCC=6.0V；CL=50pF | 11 |
| 建立时间 Dn到LE (Setup time) | tsu | 50 | 14 | | ns | Dn到LE；见图10；VCC=2.0V；CL=50pF | 11 |
| 建立时间 Dn到LE (Setup time) | tsu | 10 | 5 | | ns | Dn到LE；见图10；VCC=4.5V；CL=50pF | 11 |
| 建立时间 Dn到LE (Setup time) | tsu | 9 | 4 | | ns | Dn到LE；见图10；VCC=6.0V；CL=50pF | 11 |
| 保持时间 Dn到LE (Hold time) | th | 5 | -8 | | ns | Dn到LE；见图10；VCC=2.0V；CL=50pF | 11 |
| 保持时间 Dn到LE (Hold time) | th | 5 | -3 | | ns | Dn到LE；见图10；VCC=4.5V；CL=50pF | 11 |
| 保持时间 Dn到LE (Hold time) | th | 5 | -2 | | ns | Dn到LE；见图10；VCC=6.0V；CL=50pF | 11 |
## CAD (KiCad official)
- Symbol: `SN74HC373D`
- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`
- 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `sn74hc373d-etched.step` / `sn74hc373d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc373d.step` / `sn74hc373d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590923054564929536) (22 pp, sha256 `0f3c8499ba7a7a92`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hc373d-datasheet.pdf)