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SN74HC32 Quad OR Gate
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Quad 2-input OR gate in the 74HC CMOS family.
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sn74hc32: laser-etched CAD + chip hero (factory 2.0.0 backfill)
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SN74HC32
Texas Instruments · Logic Gate · SOIC-14
The SN74HC32 contains four independent 2-input OR gates in the 74HC CMOS logic family. Each output goes high when either input is high, useful for combining interrupt or status lines and general glue logic.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1, Input A. Logic input for the first 2-input OR gate. VIH >= 4.2 V and VIL <= 1.8 V at VCC = 6 V. |
| 2 | 1B | input | Channel 1, Input B. Second logic input for OR gate 1. Buffered CMOS input; VIH/VIL scale with VCC per Recommended Operating Conditions. |
| 3 | 1Y | output | Channel 1, Output Y. 1Y = 1A + 1B. Drives up to 10 LSTTL loads; VOH >= 5.48 V and VOL <= 0.33 V at VCC = 6 V. |
| 4 | 2A | input | Channel 2, Input A. Logic input for the second 2-input OR gate. |
| 5 | 2B | input | Channel 2, Input B. Second logic input for OR gate 2. |
| 6 | 2Y | output | Channel 2, Output Y. 2Y = 2A + 2B. |
| 7 | GND | power_in | Ground reference (0 V) for the device. Connect to system ground with a low-inductance return. |
| 8 | 3Y | output | Channel 3, Output Y. 3Y = 3A + 3B. |
| 9 | 3A | input | Channel 3, Input A. Logic input for the third 2-input OR gate. |
| 10 | 3B | input | Channel 3, Input B. Second logic input for OR gate 3. |
| 11 | 4Y | output | Channel 4, Output Y. 4Y = 4A + 4B. |
| 12 | 4A | input | Channel 4, Input A. Logic input for the fourth 2-input OR gate. |
| 13 | 4B | input | Channel 4, Input B. Second logic input for OR gate 4. |
| 14 | VCC | power_in | Positive supply. Operating range 2 V to 6 V (5 V nominal); absolute maximum 7 V. Bypass with a 0.1 uF ceramic capacitor to GND close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Type | Quad 2-input OR gate |
| Logic family | 74HC (CMOS) |
| Supply voltage | 2 V to 6 V |
| Output current | +-5.2 mA at VCC = 4.5 V |
| Propagation delay | 9 ns typ at 5 V |
| Operating temperature | -40 C to 85 C |
Ordering variants
Same part, different packaging or reel option.
SN74HC32DSN74HC32DBSN74HC32NSN74HC32NSSN74HC32PWSN74HC32JSN74HC32WSN74HC32FK
CAD (KiCad official)
- Symbol:
sn74hc32.kicad_sym - Footprint:
sn74hc32.kicad_mod - 3D model: SOIC-14 body from KiCad
Package_SO/SOIC-14_3.9x8.7mm_P1.27mm. - 3D model files:
sn74hc32-etched.step/sn74hc32-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc32.step/sn74hc32.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
f64e03a2a4c72baf, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HC32
**Texas Instruments** · Logic Gate · SOIC-14
The SN74HC32 contains four independent 2-input OR gates in the 74HC CMOS logic family. Each output goes high when either input is high, useful for combining interrupt or status lines and general glue logic.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1, Input A. Logic input for the first 2-input OR gate. VIH >= 4.2 V and VIL <= 1.8 V at VCC = 6 V. |
| 2 | 1B | input | Channel 1, Input B. Second logic input for OR gate 1. Buffered CMOS input; VIH/VIL scale with VCC per Recommended Operating Conditions. |
| 3 | 1Y | output | Channel 1, Output Y. 1Y = 1A + 1B. Drives up to 10 LSTTL loads; VOH >= 5.48 V and VOL <= 0.33 V at VCC = 6 V. |
| 4 | 2A | input | Channel 2, Input A. Logic input for the second 2-input OR gate. |
| 5 | 2B | input | Channel 2, Input B. Second logic input for OR gate 2. |
| 6 | 2Y | output | Channel 2, Output Y. 2Y = 2A + 2B. |
| 7 | GND | power_in | Ground reference (0 V) for the device. Connect to system ground with a low-inductance return. |
| 8 | 3Y | output | Channel 3, Output Y. 3Y = 3A + 3B. |
| 9 | 3A | input | Channel 3, Input A. Logic input for the third 2-input OR gate. |
| 10 | 3B | input | Channel 3, Input B. Second logic input for OR gate 3. |
| 11 | 4Y | output | Channel 4, Output Y. 4Y = 4A + 4B. |
| 12 | 4A | input | Channel 4, Input A. Logic input for the fourth 2-input OR gate. |
| 13 | 4B | input | Channel 4, Input B. Second logic input for OR gate 4. |
| 14 | VCC | power_in | Positive supply. Operating range 2 V to 6 V (5 V nominal); absolute maximum 7 V. Bypass with a 0.1 uF ceramic capacitor to GND close to the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Type | Quad 2-input OR gate |
| Logic family | 74HC (CMOS) |
| Supply voltage | 2 V to 6 V |
| Output current | +-5.2 mA at VCC = 4.5 V |
| Propagation delay | 9 ns typ at 5 V |
| Operating temperature | -40 C to 85 C |
## Ordering variants
Same part, different packaging or reel option.
- `SN74HC32D`
- `SN74HC32DB`
- `SN74HC32N`
- `SN74HC32NS`
- `SN74HC32PW`
- `SN74HC32J`
- `SN74HC32W`
- `SN74HC32FK`
## CAD (KiCad official)
- Symbol: `sn74hc32.kicad_sym`
- Footprint: `sn74hc32.kicad_mod`
- 3D model: SOIC-14 body from KiCad `Package_SO/SOIC-14_3.9x8.7mm_P1.27mm`.
- 3D model files: `sn74hc32-etched.step` / `sn74hc32-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc32.step` / `sn74hc32.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74hc32.pdf) (38 pp, sha256 `f64e03a2a4c72baf`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hc32-datasheet.pdf)