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SN74HC273QPWRQ1
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# SN74HC273QPWRQ1++**Texas Instruments** · Flip Flops · TSSOP-20++SN74HC273QPWRQ1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLR | input | Active-low direct clear input; when low it forces all Q outputs low regardless of CLK and D. |+| 2 | 1Q | output | Single-rail output of flip-flop 1, which takes the value of 1D on the positive-going CLK edge. |+| 3 | 1D | input | Data input to flip-flop 1, which must meet the setup and hold time requirements relative to the positive-going CLK edge. |+| 4 | 2D | input | Data input to flip-flop 2, which must meet the setup and hold time requirements relative to the positive-going CLK edge. |+| 5 | 2Q | output | Single-rail output of flip-flop 2, which takes the value of 2D on the positive-going CLK edge. |+| 6 | 3Q | output | Single-rail output of flip-flop 3, which takes the value of 3D on the positive-going CLK edge. |+| 7 | 3D | input | Data input to flip-flop 3, which must meet the setup and hold time requirements relative to the positive-going CLK edge. |+| 8 | 4D | input | Data input to flip-flop 4, which must meet the setup and hold time requirements relative to the positive-going CLK edge. |+| 9 | 4Q | output | Single-rail output of flip-flop 4, which takes the value of 4D on the positive-going CLK edge. |+| 10 | GND | power_in | Device ground reference pin. |+| 11 | CLK | input | Clock input; data is transferred to the Q outputs on the positive-going edge, and D has no effect while CLK is high or low. |+| 12 | 5Q | output | Single-rail output of flip-flop 5, which takes the value of 5D on the positive-going CLK edge. |+| 13 | 5D | input | Data input to flip-flop 5, which must meet the setup and hold time requirements relative to the positive-going CLK edge. |+| 14 | 6D | input | Data input to flip-flop 6, which must meet the setup and hold time requirements relative to the positive-going CLK edge. |+| 15 | 6Q | output | Single-rail output of flip-flop 6, which takes the value of 6D on the positive-going CLK edge. |+| 16 | 7Q | output | Single-rail output of flip-flop 7, which takes the value of 7D on the positive-going CLK edge. |+| 17 | 7D | input | Data input to flip-flop 7, which must meet the setup and hold time requirements relative to the positive-going CLK edge. |+| 18 | 8D | input | Data input to flip-flop 8, which must meet the setup and hold time requirements relative to the positive-going CLK edge. |+| 19 | 8Q | output | Single-rail output of flip-flop 8, which takes the value of 8D on the positive-going CLK edge. |+| 20 | VCC | power_in | Supply voltage pin; the recommended operating range is 2 V to 6 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74HC273QPWRQ1`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `sn74hc273qpwrq1-etched.step` / `sn74hc273qpwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc273qpwrq1.step` / `sn74hc273qpwrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hc273-q1) (16 pp, sha256 `d61ed979e031facb`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74hc273qpwrq1-datasheet.pdf)
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when low it forces all Q outputs low regardless of CLK and D."+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "output",+ "description": "Single-rail output of flip-flop 1, which takes the value of 1D on the positive-going CLK edge."+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "Data input to flip-flop 1, which must meet the setup and hold time requirements relative to the positive-going CLK edge."+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "Data input to flip-flop 2, which must meet the setup and hold time requirements relative to the positive-going CLK edge."+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "output",+ "description": "Single-rail output of flip-flop 2, which takes the value of 2D on the positive-going CLK edge."+ },+ {+ "number": "6",+ "name": "3Q",+ "type": "output",+ "description": "Single-rail output of flip-flop 3, which takes the value of 3D on the positive-going CLK edge."+ },+ {+ "number": "7",+ "name": "3D",+ "type": "input",+ "description": "Data input to flip-flop 3, which must meet the setup and hold time requirements relative to the positive-going CLK edge."+ },+ {+ "number": "8",+ "name": "4D",+ "type": "input",+ "description": "Data input to flip-flop 4, which must meet the setup and hold time requirements relative to the positive-going CLK edge."+ },+ {+ "number": "9",+ "name": "4Q",+ "type": "output",+ "description": "Single-rail output of flip-flop 4, which takes the value of 4D on the positive-going CLK edge."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground reference pin."+ },+ {+ "number": "11",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; data is transferred to the Q outputs on the positive-going edge, and D has no effect while CLK is high or low."+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "output",+ "description": "Single-rail output of flip-flop 5, which takes the value of 5D on the positive-going CLK edge."+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "Data input to flip-flop 5, which must meet the setup and hold time requirements relative to the positive-going CLK edge."+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "Data input to flip-flop 6, which must meet the setup and hold time requirements relative to the positive-going CLK edge."+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "output",+ "description": "Single-rail output of flip-flop 6, which takes the value of 6D on the positive-going CLK edge."+ },+ {+ "number": "16",+ "name": "7Q",+ "type": "output",+ "description": "Single-rail output of flip-flop 7, which takes the value of 7D on the positive-going CLK edge."+ },+ {+ "number": "17",+ "name": "7D",+ "type": "input",+ "description": "Data input to flip-flop 7, which must meet the setup and hold time requirements relative to the positive-going CLK edge."+ },+ {+ "number": "18",+ "name": "8D",+ "type": "input",+ "description": "Data input to flip-flop 8, which must meet the setup and hold time requirements relative to the positive-going CLK edge."+ },+ {+ "number": "19",+ "name": "8Q",+ "type": "output",+ "description": "Single-rail output of flip-flop 8, which takes the value of 8D on the positive-going CLK edge."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage pin; the recommended operating range is 2 V to 6 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin numbers were taken from the TOP VIEW pin-name listing on page 1 (pins 1-10 down the left, 20-11 "+ ],+ "pages_sent": 16,+ "cost_usd": 0.0719,+ "at": "2026-10-08T16:11:45"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74hc273-q1",+ "pages": 16,+ "sha256": "d61ed979e031facb",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74hc273qpwrq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74hc273qpwrq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "c343add6342438e345e06c5ae558753654c5c48eafcec9d2cf4db4f3ff76089b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}