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Contents

README

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SN74HC273N

Texas Instruments · Flip Flops · DIP-20

SN74HC273N from Texas Instruments, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active low clear input; when low, forces all Q outputs low regardless of clock or data inputs
2 1Q output Output of flip-flop 1; can drive up to 10 LSTTL loads with ±4 mA output drive at 5V
3 1D input Data input for flip-flop 1; sampled on rising edge of CLK when CLR is inactive; meets setup and hold time requirements of section 6.8
4 2D input Data input for flip-flop 2; sampled on rising edge of CLK when CLR is inactive; meets setup and hold time requirements of section 6.8
5 2Q output Output of flip-flop 2; can drive up to 10 LSTTL loads with ±4 mA output drive at 5V
6 3Q output Output of flip-flop 3; can drive up to 10 LSTTL loads with ±4 mA output drive at 5V
7 3D input Data input for flip-flop 3; sampled on rising edge of CLK when CLR is inactive; meets setup and hold time requirements of section 6.8
8 4D input Data input for flip-flop 4; sampled on rising edge of CLK when CLR is inactive; meets setup and hold time requirements of section 6.8
9 4Q output Output of flip-flop 4; can drive up to 10 LSTTL loads with ±4 mA output drive at 5V
10 GND power_in Ground reference voltage
11 CLK input Clock input; rising edge triggers data transfer from D inputs to Q outputs; maximum frequency and minimum pulse duration requirements in section 6.8
12 5Q output Output of flip-flop 5; can drive up to 10 LSTTL loads with ±4 mA output drive at 5V
13 5D input Data input for flip-flop 5; sampled on rising edge of CLK when CLR is inactive; meets setup and hold time requirements of section 6.8
14 6D input Data input for flip-flop 6; sampled on rising edge of CLK when CLR is inactive; meets setup and hold time requirements of section 6.8
15 6Q output Output of flip-flop 6; can drive up to 10 LSTTL loads with ±4 mA output drive at 5V
16 7Q output Output of flip-flop 7; can drive up to 10 LSTTL loads with ±4 mA output drive at 5V
17 7D input Data input for flip-flop 7; sampled on rising edge of CLK when CLR is inactive; meets setup and hold time requirements of section 6.8
18 8D input Data input for flip-flop 8; sampled on rising edge of CLK when CLR is inactive; meets setup and hold time requirements of section 6.8
19 8Q output Output of flip-flop 8; can drive up to 10 LSTTL loads with ±4 mA output drive at 5V
20 VCC power_out Power supply; operating voltage range 2V to 6V per section 6.3 recommended operating conditions

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HC273N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: DIP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hc273n-etched.step / sn74hc273n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc273n.step / sn74hc273n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 c8f36a86a0f545d8, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF