component

SN74HC273DBR

Public Made by Adom

by adom

Texas Instruments Flip Flops, SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74hc273dbrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers sn74hc273dbr: viewers · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
sn74hc273dbr-etched.glb Publish 0.1.0 · Ray 5d ago
sn74hc273dbr-etched.step sn74hc273dbr: factory component page (tier=mfr) · Ray 5d ago
sn74hc273dbr-hero.glb sn74hc273dbr: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
sn74hc273dbr-hero.overlay.json Publish 0.1.0 · Ray 5d ago
sn74hc273dbr.glb Publish 0.1.0 · Ray 5d ago
sn74hc273dbr.kicad_mod Publish 0.1.0 · Ray 5d ago
sn74hc273dbr.kicad_sym Publish 0.1.0 · Ray 5d ago
sn74hc273dbr.lbr Publish 0.1.0 · Ray 5d ago
sn74hc273dbr.step Publish 0.1.0 · Ray 5d ago

SN74HC273DBR

Texas Instruments · Flip Flops · SSOP-20-208mil

SN74HC273DBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low direct clear input (CLR) that resets the flip-flops independently of the clock.
2 1Q output Output 1 of the positive-edge-triggered D flip-flop, which takes the D input value on the rising edge of CLK.
3 1D input Data input 1; data meeting the setup-time requirement is transferred to 1Q on the positive CLK edge.
4 2D input Data input 2; data meeting the setup-time requirement is transferred to 2Q on the positive CLK edge.
5 2Q output Output 2 of the positive-edge-triggered D flip-flop.
6 3Q output Output 3 of the positive-edge-triggered D flip-flop.
7 3D input Data input 3; data meeting the setup-time requirement is transferred to 3Q on the positive CLK edge.
8 4D input Data input 4; data meeting the setup-time requirement is transferred to 4Q on the positive CLK edge.
9 4Q output Output 4 of the positive-edge-triggered D flip-flop.
10 GND power_in Ground reference pin for the device.
11 CLK input Clock input; the Q outputs update on the positive edge of CLK, and D has no effect while CLK is held high or low.
12 5Q output Output 5 of the positive-edge-triggered D flip-flop.
13 5D input Data input 5; data meeting the setup-time requirement is transferred to 5Q on the positive CLK edge.
14 6D input Data input 6; data meeting the setup-time requirement is transferred to 6Q on the positive CLK edge.
15 6Q output Output 6 of the positive-edge-triggered D flip-flop.
16 7Q output Output 7 of the positive-edge-triggered D flip-flop.
17 7D input Data input 7; data meeting the setup-time requirement is transferred to 7Q on the positive CLK edge.
18 8D input Data input 8; data meeting the setup-time requirement is transferred to 8Q on the positive CLK edge.
19 8Q output Output 8 of the positive-edge-triggered D flip-flop.
20 VCC power_in Positive supply pin; the recommended supply range is 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20-208mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 2 5 6 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input voltage VI 0 V 4
Input transition rise and fall time Δt/Δv 1000 ns VCC = 2 V 4
Input transition rise and fall time Δt/Δv 500 ns VCC = 4.5 V 4
Input transition rise and fall time Δt/Δv 400 ns VCC = 6 V 4
Operating free-air temperature TA -40 85 °C SN74HC273 4
High-level output voltage VOH 1.9 V VI = VIH or VIL, IOH = -20 µA, VCC = 2 V 6
High-level output voltage VOH 4.4 V VI = VIH or VIL, IOH = -20 µA, VCC = 4.5 V 6
High-level output voltage VOH 5.9 V VI = VIH or VIL, IOH = -20 µA, VCC = 6 V 6
High-level output voltage VOH 3.84 V VI = VIH or VIL, IOH = -4 mA, VCC = 4.5 V 6
High-level output voltage VOH 5.34 V VI = VIH or VIL, IOH = -5.2 mA, VCC = 6 V 6
Low-level output voltage VOL 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC = 2 V 6
Low-level output voltage VOL 0.33 V VI = VIH or VIL, IOL = 4 mA, VCC = 4.5 V 6
Input leakage current II -1000 1000 nA VI = VCC or 0, VCC = 6 V 6
Supply current ICC 80 µA VI = VCC or 0, IO = 0, VCC = 6 V 6
Input capacitance Ci 10 pF VCC = 2 V to 6 V 6
Clock frequency fclock 4 MHz VCC = 2 V 7
Clock frequency fclock 21 MHz VCC = 4.5 V 7
Clock frequency fclock 25 MHz VCC = 6 V 7
Pulse duration, CLR low tw 100 ns VCC = 2 V 7
Pulse duration, CLR low tw 20 ns VCC = 4.5 V 7
Pulse duration, CLR low tw 17 ns VCC = 6 V 7
Pulse duration, CLK high or low tw 100 ns VCC = 2 V 7
Pulse duration, CLK high or low tw 20 ns VCC = 4.5 V 7
Pulse duration, CLK high or low tw 17 ns VCC = 6 V 7
Setup time before CLK↑, data tsu 125 ns VCC = 2 V 7
Setup time before CLK↑, data tsu 25 ns VCC = 4.5 V 7
Setup time before CLK↑, data tsu 21 ns VCC = 6 V 7
Setup time before CLK↑, CLR inactive tsu 125 ns VCC = 2 V 7
Setup time before CLK↑, CLR inactive tsu 25 ns VCC = 4.5 V 7
Setup time before CLK↑, CLR inactive tsu 21 ns VCC = 6 V 7
Hold time, data after CLK↑ th 0 ns VCC = 2 V 7
tPHL, from CLR to any output tPHL 200 ns CL = 50 pF, VCC = 2 V 8
tPHL, from CLR to any output tPHL 40 ns CL = 50 pF, VCC = 4.5 V 8
tPHL, from CLR to any output tPHL 34 ns CL = 50 pF, VCC = 6 V 8
tpd, from CLK to any output tpd 200 ns CL = 50 pF, VCC = 2 V 8
tpd, from CLK to any output tpd 40 ns CL = 50 pF, VCC = 4.5 V 8
tpd, from CLK to any output tpd 34 ns CL = 50 pF, VCC = 6 V 8
tt, to any output tt 95 ns CL = 50 pF, VCC = 2 V 9
tt, to any output tt 19 ns CL = 50 pF, VCC = 4.5 V 9
tt, to any output tt 16 ns CL = 50 pF, VCC = 6 V 9
Junction-to-ambient thermal resistance (DB, SSOP-20) RθJA 122.7 °C/W DB (SSOP) 20-pin package 5

CAD (KiCad official)

  • Symbol: SN74HC273DBR
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74hc273dbr-etched.step / sn74hc273dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc273dbr.step / sn74hc273dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 5f99e4392c073ec0, retrieved 2026-10-18, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF