component
SN74HC273D
Public Made by Adomby adom
lingxingic Flip Flops, SOP-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74HC273D
lingxingic · Flip Flops · SOP-20-300mil
SN74HC273D from lingxingic, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Master reset input, active low; when low, all Qn outputs go low regardless of CP and Dn. |
| 2 | Q0 | output | Flip-flop 0 output, following D0 on the rising edge of CP. |
| 3 | D0 | input | Data input for flip-flop 0, sampled on the rising edge of CP within the specified setup and hold times. |
| 4 | D1 | input | Data input for flip-flop 1, sampled on the rising edge of CP within the specified setup and hold times. |
| 5 | Q1 | output | Flip-flop 1 output, following D1 on the rising edge of CP. |
| 6 | Q2 | output | Flip-flop 2 output, following D2 on the rising edge of CP. |
| 7 | D2 | input | Data input for flip-flop 2, sampled on the rising edge of CP within the specified setup and hold times. |
| 8 | D3 | input | Data input for flip-flop 3, sampled on the rising edge of CP within the specified setup and hold times. |
| 9 | Q3 | output | Flip-flop 3 output, following D3 on the rising edge of CP. |
| 10 | GND | power_in | Ground reference (0 V). |
| 11 | CP | input | Clock input; data is loaded on the rising edge. |
| 12 | Q4 | output | Flip-flop 4 output, following D4 on the rising edge of CP. |
| 13 | D4 | input | Data input for flip-flop 4, sampled on the rising edge of CP within the specified setup and hold times. |
| 14 | D5 | input | Data input for flip-flop 5, sampled on the rising edge of CP within the specified setup and hold times. |
| 15 | Q5 | output | Flip-flop 5 output, following D5 on the rising edge of CP. |
| 16 | Q6 | output | Flip-flop 6 output, following D6 on the rising edge of CP. |
| 17 | D6 | input | Data input for flip-flop 6, sampled on the rising edge of CP within the specified setup and hold times. |
| 18 | D7 | input | Data input for flip-flop 7, sampled on the rising edge of CP within the specified setup and hold times. |
| 19 | Q7 | output | Flip-flop 7 output, following D7 on the rising edge of CP. |
| 20 | VCC | power_in | Supply voltage: 2.0-6.0 V for SN74HC273, 4.5-5.5 V for SN74HCT273 (recommended operating range). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 Supply voltage (absolute max) | VCC | -0.5 | 7 | V | 8 | ||
| 输入钳位电流 Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 8 | |
| 输出钳位电流 Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 8 | |
| 输出电流 Output current | IO | -25 | 25 | mA | -0.5V<VO<VCC+0.5V | 8 | |
| 电源电流 Supply current (absolute max) | ICC | 50 | mA | 8 | |||
| 地电流 Ground current (absolute max) | IGND | -50 | mA | 8 | |||
| 贮存温度 Storage temperature | Tstg | -65 | 150 | ℃ | 8 | ||
| 总功耗 Total power dissipation | Ptot | 500 | mW | 8 | |||
| 焊接温度 Soldering temperature (SOP/TSSOP/SOP(M)) | TL | 260 | ℃ | 10 s; SOP/TSSOP/SOP(M) | 8 | ||
| 电源电压 Supply voltage (recommended, SN74HC273) | VCC | 2 | 5 | 6 | V | 9 | |
| 输入上升和下降转换速率 Input rise/fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 9 | ||
| 输入上升和下降转换速率 Input rise/fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 9 | |
| 输入上升和下降转换速率 Input rise/fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 9 | ||
| 工作环境温度 Operating ambient temperature | Tamb | -40 | 125 | ℃ | 9 | ||
| 高电平输入电压 High-level input voltage | VIH | 1.5 | V | Tamb=-40~+125℃; VCC=2.0V | 12 | ||
| 高电平输入电压 High-level input voltage | VIH | 3.15 | V | Tamb=-40~+125℃; VCC=4.5V | 12 | ||
| 高电平输入电压 High-level input voltage | VIH | 4.2 | V | Tamb=-40~+125℃; VCC=6.0V | 12 | ||
| 低电平输入电压 Low-level input voltage | VIL | 0.5 | V | Tamb=-40~+125℃; VCC=2.0V | 12 | ||
| 低电平输入电压 Low-level input voltage | VIL | 1.35 | V | Tamb=-40~+125℃; VCC=4.5V | 12 | ||
| 低电平输入电压 Low-level input voltage | VIL | 1.8 | V | Tamb=-40~+125℃; VCC=6.0V | 12 | ||
| 高电平输出电压 High-level output voltage | VOH | 1.9 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-20uA; VCC=2.0V | 12 | ||
| 高电平输出电压 High-level output voltage | VOH | 4.4 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-20uA; VCC=4.5V | 12 | ||
| 高电平输出电压 High-level output voltage | VOH | 5.9 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-20uA; VCC=6.0V | 12 | ||
| 高电平输出电压 High-level output voltage | VOH | 3.7 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-4.0mA; VCC=4.5V | 12 | ||
| 高电平输出电压 High-level output voltage | VOH | 5.2 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-5.2mA; VCC=6.0V | 12 | ||
| 低电平输出电压 Low-level output voltage | VOL | 0.1 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=20uA; VCC=2.0V | 12 | ||
| 低电平输出电压 Low-level output voltage | VOL | 0.4 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=4.0mA; VCC=4.5V | 12 | ||
| 输入漏电流 Input leakage current | II | -1 | 1 | uA | Tamb=-40~+125℃; VI=VCC或GND; VCC=6.0V | 12 | |
| 静态电流 Quiescent supply current | ICC | 160 | uA | Tamb=-40~+125℃; VI=VCC或GND; IO=0A; VCC=6.0V | 12 | ||
| CP到Qn的传输延时 Propagation delay CP to Qn | tpd | 225 | ns | Tamb=-40~+125℃; CL=50pF; 见图6; VCC=2.0V | 17 | ||
| CP到Qn的传输延时 Propagation delay CP to Qn | tpd | 45 | ns | Tamb=-40~+125℃; CL=50pF; 见图6; VCC=4.5V | 17 | ||
| CP到Qn的传输延时 Propagation delay CP to Qn | tpd | 38 | ns | Tamb=-40~+125℃; CL=50pF; 见图6; VCC=6.0V | 17 | ||
| MR到Qn高电平到低电平的传输延时 Propagation delay MR to Qn (high-to-low) | tPHL | 225 | ns | Tamb=-40~+125℃; CL=50pF; 见图7; VCC=2.0V | 17 | ||
| MR到Qn高电平到低电平的传输延时 Propagation delay MR to Qn (high-to-low) | tPHL | 45 | ns | Tamb=-40~+125℃; CL=50pF; 见图7; VCC=4.5V | 17 | ||
| MR到Qn高电平到低电平的传输延时 Propagation delay MR to Qn (high-to-low) | tPHL | 38 | ns | Tamb=-40~+125℃; CL=50pF; 见图7; VCC=6.0V | 17 | ||
| 转换时间 Output transition time | tt | 110 | ns | Tamb=-40~+125℃; CL=50pF; Qn输出; 见图6; VCC=2.0V | 17 | ||
| 转换时间 Output transition time | tt | 22 | ns | Tamb=-40~+125℃; CL=50pF; Qn输出; 见图6; VCC=4.5V | 17 | ||
| 转换时间 Output transition time | tt | 19 | ns | Tamb=-40~+125℃; CL=50pF; Qn输出; 见图6; VCC=6.0V | 18 | ||
| CP脉冲宽度 Clock pulse width (high or low) | tW | 120 | ns | Tamb=-40~+125℃; CL=50pF; CP输入高电平或低电平; 见图6; VCC=2.0V | 17 | ||
| CP脉冲宽度 Clock pulse width (high or low) | tW | 24 | ns | Tamb=-40~+125℃; CL=50pF; CP输入高电平或低电平; 见图6; VCC=4.5V | 17 | ||
| CP脉冲宽度 Clock pulse width (high or low) | tW | 20 | ns | Tamb=-40~+125℃; CL=50pF; CP输入高电平或低电平; 见图6; VCC=6.0V | 18 | ||
| MR脉冲宽度(低电平) MR pulse width (low) | tW | 90 | ns | Tamb=-40~+125℃; CL=50pF; MR输入低电平; 见图7; VCC=2.0V | 18 | ||
| MR脉冲宽度(低电平) MR pulse width (low) | tW | 18 | ns | Tamb=-40~+125℃; CL=50pF; MR输入低电平; 见图7; VCC=4.5V | 18 | ||
| MR脉冲宽度(低电平) MR pulse width (low) | tW | 15 | ns | Tamb=-40~+125℃; CL=50pF; MR输入低电平; 见图7; VCC=6.0V | 18 | ||
| 恢复时间 Recovery time MR to CP | trec | 75 | ns | Tamb=-40~+125℃; CL=50pF; MR到CP; 见图7; VCC=2.0V | 18 | ||
| 恢复时间 Recovery time MR to CP | trec | 15 | ns | Tamb=-40~+125℃; CL=50pF; MR到CP; 见图7; VCC=4.5V | 18 | ||
| 恢复时间 Recovery time MR to CP | trec | 13 | ns | Tamb=-40~+125℃; CL=50pF; MR到CP; 见图7; VCC=6.0V | 18 | ||
| 建立时间 Setup time Dn to CP | tsu | 90 | ns | Tamb=-40~+125℃; CL=50pF; Dn到CP; 见图8; VCC=2.0V | 18 | ||
| 建立时间 Setup time Dn to CP | tsu | 18 | ns | Tamb=-40~+125℃; CL=50pF; Dn到CP; 见图8; VCC=4.5V | 18 | ||
| 建立时间 Setup time Dn to CP | tsu | 15 | ns | Tamb=-40~+125℃; CL=50pF; Dn到CP; 见图8; VCC=6.0V | 18 | ||
| 保持时间 Hold time Dn to CP | th | 3 | ns | Tamb=-40~+125℃; CL=50pF; Dn到CP; 见图8; VCC=2.0V | 18 | ||
| 最大频率 Maximum clock frequency | fmax | 4 | MHz | Tamb=-40~+125℃; CL=50pF; CP输入; 见图6; VCC=2.0V | 18 | ||
| 最大频率 Maximum clock frequency | fmax | 20 | MHz | Tamb=-40~+125℃; CL=50pF; CP输入; 见图6; VCC=4.5V | 18 | ||
| 最大频率 Maximum clock frequency | fmax | 24 | MHz | Tamb=-40~+125℃; CL=50pF; CP输入; 见图6; VCC=6.0V | 18 |
CAD (KiCad official)
- Symbol:
SN74HC273D - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
sn74hc273d-etched.step/sn74hc273d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc273d.step/sn74hc273d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (27 pp, sha256
a26108f4267548db, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HC273D
**lingxingic** · Flip Flops · SOP-20-300mil
SN74HC273D from lingxingic, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Master reset input, active low; when low, all Qn outputs go low regardless of CP and Dn. |
| 2 | Q0 | output | Flip-flop 0 output, following D0 on the rising edge of CP. |
| 3 | D0 | input | Data input for flip-flop 0, sampled on the rising edge of CP within the specified setup and hold times. |
| 4 | D1 | input | Data input for flip-flop 1, sampled on the rising edge of CP within the specified setup and hold times. |
| 5 | Q1 | output | Flip-flop 1 output, following D1 on the rising edge of CP. |
| 6 | Q2 | output | Flip-flop 2 output, following D2 on the rising edge of CP. |
| 7 | D2 | input | Data input for flip-flop 2, sampled on the rising edge of CP within the specified setup and hold times. |
| 8 | D3 | input | Data input for flip-flop 3, sampled on the rising edge of CP within the specified setup and hold times. |
| 9 | Q3 | output | Flip-flop 3 output, following D3 on the rising edge of CP. |
| 10 | GND | power_in | Ground reference (0 V). |
| 11 | CP | input | Clock input; data is loaded on the rising edge. |
| 12 | Q4 | output | Flip-flop 4 output, following D4 on the rising edge of CP. |
| 13 | D4 | input | Data input for flip-flop 4, sampled on the rising edge of CP within the specified setup and hold times. |
| 14 | D5 | input | Data input for flip-flop 5, sampled on the rising edge of CP within the specified setup and hold times. |
| 15 | Q5 | output | Flip-flop 5 output, following D5 on the rising edge of CP. |
| 16 | Q6 | output | Flip-flop 6 output, following D6 on the rising edge of CP. |
| 17 | D6 | input | Data input for flip-flop 6, sampled on the rising edge of CP within the specified setup and hold times. |
| 18 | D7 | input | Data input for flip-flop 7, sampled on the rising edge of CP within the specified setup and hold times. |
| 19 | Q7 | output | Flip-flop 7 output, following D7 on the rising edge of CP. |
| 20 | VCC | power_in | Supply voltage: 2.0-6.0 V for SN74HC273, 4.5-5.5 V for SN74HCT273 (recommended operating range). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 Supply voltage (absolute max) | VCC | -0.5 | | 7 | V | | 8 |
| 输入钳位电流 Input clamp current | IIK | -20 | | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 8 |
| 输出钳位电流 Output clamp current | IOK | -20 | | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 8 |
| 输出电流 Output current | IO | -25 | | 25 | mA | -0.5V<VO<VCC+0.5V | 8 |
| 电源电流 Supply current (absolute max) | ICC | | | 50 | mA | | 8 |
| 地电流 Ground current (absolute max) | IGND | -50 | | | mA | | 8 |
| 贮存温度 Storage temperature | Tstg | -65 | | 150 | ℃ | | 8 |
| 总功耗 Total power dissipation | Ptot | | | 500 | mW | | 8 |
| 焊接温度 Soldering temperature (SOP/TSSOP/SOP(M)) | TL | | | 260 | ℃ | 10 s; SOP/TSSOP/SOP(M) | 8 |
| 电源电压 Supply voltage (recommended, SN74HC273) | VCC | 2 | 5 | 6 | V | | 9 |
| 输入上升和下降转换速率 Input rise/fall rate | Δt/ΔV | | | 625 | ns/V | VCC=2.0V | 9 |
| 输入上升和下降转换速率 Input rise/fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC=4.5V | 9 |
| 输入上升和下降转换速率 Input rise/fall rate | Δt/ΔV | | | 83 | ns/V | VCC=6.0V | 9 |
| 工作环境温度 Operating ambient temperature | Tamb | -40 | | 125 | ℃ | | 9 |
| 高电平输入电压 High-level input voltage | VIH | 1.5 | | | V | Tamb=-40~+125℃; VCC=2.0V | 12 |
| 高电平输入电压 High-level input voltage | VIH | 3.15 | | | V | Tamb=-40~+125℃; VCC=4.5V | 12 |
| 高电平输入电压 High-level input voltage | VIH | 4.2 | | | V | Tamb=-40~+125℃; VCC=6.0V | 12 |
| 低电平输入电压 Low-level input voltage | VIL | | | 0.5 | V | Tamb=-40~+125℃; VCC=2.0V | 12 |
| 低电平输入电压 Low-level input voltage | VIL | | | 1.35 | V | Tamb=-40~+125℃; VCC=4.5V | 12 |
| 低电平输入电压 Low-level input voltage | VIL | | | 1.8 | V | Tamb=-40~+125℃; VCC=6.0V | 12 |
| 高电平输出电压 High-level output voltage | VOH | 1.9 | | | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-20uA; VCC=2.0V | 12 |
| 高电平输出电压 High-level output voltage | VOH | 4.4 | | | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-20uA; VCC=4.5V | 12 |
| 高电平输出电压 High-level output voltage | VOH | 5.9 | | | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-20uA; VCC=6.0V | 12 |
| 高电平输出电压 High-level output voltage | VOH | 3.7 | | | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-4.0mA; VCC=4.5V | 12 |
| 高电平输出电压 High-level output voltage | VOH | 5.2 | | | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-5.2mA; VCC=6.0V | 12 |
| 低电平输出电压 Low-level output voltage | VOL | | | 0.1 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=20uA; VCC=2.0V | 12 |
| 低电平输出电压 Low-level output voltage | VOL | | | 0.4 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=4.0mA; VCC=4.5V | 12 |
| 输入漏电流 Input leakage current | II | -1 | | 1 | uA | Tamb=-40~+125℃; VI=VCC或GND; VCC=6.0V | 12 |
| 静态电流 Quiescent supply current | ICC | | | 160 | uA | Tamb=-40~+125℃; VI=VCC或GND; IO=0A; VCC=6.0V | 12 |
| CP到Qn的传输延时 Propagation delay CP to Qn | tpd | | | 225 | ns | Tamb=-40~+125℃; CL=50pF; 见图6; VCC=2.0V | 17 |
| CP到Qn的传输延时 Propagation delay CP to Qn | tpd | | | 45 | ns | Tamb=-40~+125℃; CL=50pF; 见图6; VCC=4.5V | 17 |
| CP到Qn的传输延时 Propagation delay CP to Qn | tpd | | | 38 | ns | Tamb=-40~+125℃; CL=50pF; 见图6; VCC=6.0V | 17 |
| MR到Qn高电平到低电平的传输延时 Propagation delay MR to Qn (high-to-low) | tPHL | | | 225 | ns | Tamb=-40~+125℃; CL=50pF; 见图7; VCC=2.0V | 17 |
| MR到Qn高电平到低电平的传输延时 Propagation delay MR to Qn (high-to-low) | tPHL | | | 45 | ns | Tamb=-40~+125℃; CL=50pF; 见图7; VCC=4.5V | 17 |
| MR到Qn高电平到低电平的传输延时 Propagation delay MR to Qn (high-to-low) | tPHL | | | 38 | ns | Tamb=-40~+125℃; CL=50pF; 见图7; VCC=6.0V | 17 |
| 转换时间 Output transition time | tt | | | 110 | ns | Tamb=-40~+125℃; CL=50pF; Qn输出; 见图6; VCC=2.0V | 17 |
| 转换时间 Output transition time | tt | | | 22 | ns | Tamb=-40~+125℃; CL=50pF; Qn输出; 见图6; VCC=4.5V | 17 |
| 转换时间 Output transition time | tt | | | 19 | ns | Tamb=-40~+125℃; CL=50pF; Qn输出; 见图6; VCC=6.0V | 18 |
| CP脉冲宽度 Clock pulse width (high or low) | tW | 120 | | | ns | Tamb=-40~+125℃; CL=50pF; CP输入高电平或低电平; 见图6; VCC=2.0V | 17 |
| CP脉冲宽度 Clock pulse width (high or low) | tW | 24 | | | ns | Tamb=-40~+125℃; CL=50pF; CP输入高电平或低电平; 见图6; VCC=4.5V | 17 |
| CP脉冲宽度 Clock pulse width (high or low) | tW | 20 | | | ns | Tamb=-40~+125℃; CL=50pF; CP输入高电平或低电平; 见图6; VCC=6.0V | 18 |
| MR脉冲宽度(低电平) MR pulse width (low) | tW | 90 | | | ns | Tamb=-40~+125℃; CL=50pF; MR输入低电平; 见图7; VCC=2.0V | 18 |
| MR脉冲宽度(低电平) MR pulse width (low) | tW | 18 | | | ns | Tamb=-40~+125℃; CL=50pF; MR输入低电平; 见图7; VCC=4.5V | 18 |
| MR脉冲宽度(低电平) MR pulse width (low) | tW | 15 | | | ns | Tamb=-40~+125℃; CL=50pF; MR输入低电平; 见图7; VCC=6.0V | 18 |
| 恢复时间 Recovery time MR to CP | trec | 75 | | | ns | Tamb=-40~+125℃; CL=50pF; MR到CP; 见图7; VCC=2.0V | 18 |
| 恢复时间 Recovery time MR to CP | trec | 15 | | | ns | Tamb=-40~+125℃; CL=50pF; MR到CP; 见图7; VCC=4.5V | 18 |
| 恢复时间 Recovery time MR to CP | trec | 13 | | | ns | Tamb=-40~+125℃; CL=50pF; MR到CP; 见图7; VCC=6.0V | 18 |
| 建立时间 Setup time Dn to CP | tsu | 90 | | | ns | Tamb=-40~+125℃; CL=50pF; Dn到CP; 见图8; VCC=2.0V | 18 |
| 建立时间 Setup time Dn to CP | tsu | 18 | | | ns | Tamb=-40~+125℃; CL=50pF; Dn到CP; 见图8; VCC=4.5V | 18 |
| 建立时间 Setup time Dn to CP | tsu | 15 | | | ns | Tamb=-40~+125℃; CL=50pF; Dn到CP; 见图8; VCC=6.0V | 18 |
| 保持时间 Hold time Dn to CP | th | 3 | | | ns | Tamb=-40~+125℃; CL=50pF; Dn到CP; 见图8; VCC=2.0V | 18 |
| 最大频率 Maximum clock frequency | fmax | 4 | | | MHz | Tamb=-40~+125℃; CL=50pF; CP输入; 见图6; VCC=2.0V | 18 |
| 最大频率 Maximum clock frequency | fmax | 20 | | | MHz | Tamb=-40~+125℃; CL=50pF; CP输入; 见图6; VCC=4.5V | 18 |
| 最大频率 Maximum clock frequency | fmax | 24 | | | MHz | Tamb=-40~+125℃; CL=50pF; CP输入; 见图6; VCC=6.0V | 18 |
## CAD (KiCad official)
- Symbol: `SN74HC273D`
- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`
- 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `sn74hc273d-etched.step` / `sn74hc273d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc273d.step` / `sn74hc273d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590923054384304128) (27 pp, sha256 `a26108f4267548db`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hc273d-datasheet.pdf)