SN74HC259

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74hc259",
  "title": "SN74HC259",
  "brief": "TI 8-bit addressable latch, SOIC-16. Writes one of 8 latches by address; also demux or 8-bit memory. HC 2-6 V. Datasheet-verified.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "addressable-latch",
    "latch",
    "demultiplexer",
    "74hc",
    "soic-16",
    "texas-instruments"
  ],
  "component": {
    "mpn": "SN74HC259",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic IC",
    "subcategory": "8-bit addressable latch",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc259.pdf",
    "parts": {
      "symbol": "sn74hc259.kicad_sym",
      "footprint": "sn74hc259.kicad_mod",
      "model_3d": "sn74hc259-etched.glb",
      "model_3d_plain": "sn74hc259.glb",
      "lbr": "sn74hc259.lbr",
      "model_3d_step": "sn74hc259-etched.step",
      "model_3d_step_plain": "sn74hc259.step"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "S0",
        "type": "input",
        "description": "Address select input, bit 0 (LSB). With S2/S1/S0 selects one of the eight internal latches Q0..Q7 per Table 7-2. CMOS input, VIH = 3.15 V at VCC = 4.5 V."
      },
      {
        "number": "2",
        "name": "S1",
        "type": "input",
        "description": "Address select input, bit 1. Selects the target latch together with S2 and S0."
      },
      {
        "number": "3",
        "name": "S2",
        "type": "input",
        "description": "Address select input, bit 2 (MSB). Selects the target latch together with S1 and S0."
      },
      {
        "number": "4",
        "name": "Q0",
        "type": "output",
        "description": "Active-high latch output 0. Follows D when addressed and G is low; otherwise holds its previous state. Forced low when CLR is low. Push-pull CMOS, ±4 mA drive at VCC = 5 V."
      },
      {
        "number": "5",
        "name": "Q1",
        "type": "output",
        "description": "Active-high latch output 1. Same electrical behavior as Q0."
      },
      {
        "number": "6",
        "name": "Q2",
        "type": "output",
        "description": "Active-high latch output 2. Same electrical behavior as Q0."
      },
      {
        "number": "7",
        "name": "Q3",
        "type": "output",
        "description": "Active-high latch output 3. Same electrical behavior as Q0."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). Must be tied to the system GND rail."
      },
      {
        "number": "9",
        "name": "Q4",
        "type": "output",
        "description": "Active-high latch output 4. Same electrical behavior as Q0."
      },
      {
        "number": "10",
        "name": "Q5",
        "type": "output",
        "description": "Active-high latch output 5. Same electrical behavior as Q0."
      },
      {
        "number": "11",
        "name": "Q6",
        "type": "output",
        "description": "Active-high latch output 6. Same electrical behavior as Q0."
      },
      {
        "number": "12",
        "name": "Q7",
        "type": "output",
        "description": "Active-high latch output 7. Same electrical behavior as Q0."
      },
      {
        "number": "13",
        "name": "D",
        "type": "input",
        "description": "Serial data input. Value latched into the addressed output while G is low (addressable-latch mode) or routed to the addressed output in 1-of-8 demultiplex mode."
      },
      {
        "number": "14",
        "name": "G",
        "type": "input",
        "description": "Active-low enable (write strobe). When low with CLR high, the addressed latch tracks D; when high, all latches hold their previous state (memory mode). Rising edge captures D with tsu = 15 ns, th = 5 ns at VCC = 4.5 V."
      },
      {
        "number": "15",
        "name": "CLR",
        "type": "input",
        "description": "Active-low asynchronous clear. Forces all Q0..Q7 outputs low regardless of address/data inputs. Minimum low pulse width 16 ns at VCC = 4.5 V."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply, 2 V to 6 V (5 V nominal). Decouple locally with 0.1 µF close to the pin per datasheet Section 8. ICC ≤ 80 µA at VCC = 6 V (SN74)."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74hc259.pdf",
        "pages": 31,
        "sha256": "bf1d352862715b29",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74HC259",
      "logic_family": "74HC",
      "function_code": "259",
      "function_class": "Latch",
      "function_name": "8-Bit Addressable Latch",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "sn74hc259.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74hc259-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "1aa2dba63720287c544ffde0bbdbe03814fd3daebf883a93a6c6c03e34744952",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Type": "8-bit addressable latch",
      "Latches": "8 (individually addressed)",
      "Address": "3-bit (S0-S2)",
      "Data": "D writes the selected latch",
      "Modes": "addressable latch / demux / memory",
      "Reset": "clear (CLR)",
      "Logic family": "HC (high-speed CMOS)",
      "Supply voltage": "2-6 V",
      "Package": "SOIC-16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74hc259",
    "74hc259",
    "addressable latch",
    "8-bit latch",
    "serial to parallel latch"
  ],
  "discovery_pitch": "SN74HC259 8-bit addressable latch (SOIC-16) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "sn74hc259.kicad_sym",
    "sn74hc259.kicad_mod",
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    "docs/hero.png",
    "docs/sn74hc259-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "sn74hc259-etched.step"
  ],
  "variants": [
    {
      "mpn": "SN74HC259D (SOIC-16, tube)",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC259DR (SOIC-16, tape & reel)",
      "kind": "packaging"
    }
  ]
}