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SN74HC244APWR

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Texas Instruments Buffers / Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74HC244APWR

Texas Instruments · Buffers / Drivers · TSSOP-20

SN74HC244APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for buffer 1; when low the 1A inputs pass non-inverted to the 1Y outputs, and when high the 1Y outputs are high-impedance.
2 1A1 input Data input to buffer 1 that must stay between 0 V and VCC; unused inputs must be tied to VCC or GND.
3 2Y4 output Three-state buffer output for channel 2Y4, driving up to 15 LSTTL loads with ±6 mA at 5 V.
4 1A2 input Data input to buffer 1 that must stay between 0 V and VCC; unused inputs must be tied to VCC or GND.
5 2Y3 output Three-state buffer output for channel 2Y3, driving up to 15 LSTTL loads with ±6 mA at 5 V.
6 1A3 input Data input to buffer 1 that must stay between 0 V and VCC; unused inputs must be tied to VCC or GND.
7 2Y2 output Three-state buffer output for channel 2Y2, driving up to 15 LSTTL loads with ±6 mA at 5 V.
8 1A4 input Data input to buffer 1 that must stay between 0 V and VCC; unused inputs must be tied to VCC or GND.
9 2Y1 output Three-state buffer output for channel 2Y1, driving up to 15 LSTTL loads with ±6 mA at 5 V.
10 GND power_in Ground reference for the device.
11 2A1 input Data input to buffer 2 that must stay between 0 V and VCC; unused inputs must be tied to VCC or GND.
12 1Y4 output Three-state buffer output for channel 1Y4, driving up to 15 LSTTL loads with ±6 mA at 5 V.
13 2A2 input Data input to buffer 2 that must stay between 0 V and VCC; unused inputs must be tied to VCC or GND.
14 1Y3 output Three-state buffer output for channel 1Y3, driving up to 15 LSTTL loads with ±6 mA at 5 V.
15 2A3 input Data input to buffer 2 that must stay between 0 V and VCC; unused inputs must be tied to VCC or GND.
16 1Y2 output Three-state buffer output for channel 1Y2, driving up to 15 LSTTL loads with ±6 mA at 5 V.
17 2A4 input Data input to buffer 2 that must stay between 0 V and VCC; unused inputs must be tied to VCC or GND.
18 1Y1 output Three-state buffer output for channel 1Y1, driving up to 15 LSTTL loads with ±6 mA at 5 V.
19 2OE input Active-low output enable for buffer 2; when low the 2A inputs pass non-inverted to the 2Y outputs, and when high the 2Y outputs are high-impedance.
20 VCC power_in Supply voltage, recommended 2 V to 6 V (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -35 35 mA VO = 0 or VCC 4
Continuous current through VCC or GND -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 2 5 6 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Input transition rise and fall time Δt/Δv 1000 ns/V VCC = 2 V 4
Input transition rise and fall time Δt/Δv 500 ns/V VCC = 4.5 V 4
Input transition rise and fall time Δt/Δv 400 ns/V VCC = 6 V 4
Operating free-air temperature TA -40 85 °C SN74HC244 4
Junction-to-ambient thermal resistance RθJA 131.8 °C/W PW (TSSOP) 20 pins 5
Junction-to-case (top) thermal resistance RθJC (top) 72.2 °C/W PW (TSSOP) 20 pins 5
Junction-to-board thermal resistance RθJB 82.8 °C/W PW (TSSOP) 20 pins 5
High-level output voltage VOH 1.9 V VI = VIH or VIL, IOH = -20 µA, VCC = 2 V 6
High-level output voltage VOH 4.4 V VI = VIH or VIL, IOH = -20 µA, VCC = 4.5 V 6
High-level output voltage VOH 5.9 V VI = VIH or VIL, IOH = -20 µA, VCC = 6 V 6
High-level output voltage VOH 3.84 V VI = VIH or VIL, IOH = -6 mA, VCC = 4.5 V 6
High-level output voltage VOH 5.34 V VI = VIH or VIL, IOH = -7.8 mA, VCC = 6 V 6
Low-level output voltage VOL 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC = 2 V 6
Low-level output voltage VOL 0.33 V VI = VIH or VIL, IOL = 6 mA, VCC = 4.5 V 6
Input leakage current II -1000 1000 nA VI = VCC or 0, VCC = 6 V 6
Off-state (high-impedance) output current IOZ -5 5 µA VO = VCC or 0, VI = VIH or VIL, VCC = 6 V 6
Supply current ICC 80 µA VI = VCC or 0, IO = 0, VCC = 6 V 6
Input capacitance Ci 10 pF VCC = 2 V to 6 V 6
Propagation delay, A to Y tpd 145 ns CL = 50 pF, VCC = 2 V 8
Propagation delay, A to Y tpd 29 ns CL = 50 pF, VCC = 4.5 V 8
Propagation delay, A to Y tpd 25 ns CL = 50 pF, VCC = 6 V 8
Enable time, OE to Y ten 190 ns CL = 50 pF, VCC = 2 V 8
Enable time, OE to Y ten 38 ns CL = 50 pF, VCC = 4.5 V 8
Enable time, OE to Y ten 32 ns CL = 50 pF, VCC = 6 V 8
Disable time, OE to Y tdis 190 ns CL = 50 pF, VCC = 2 V 8
Disable time, OE to Y tdis 38 ns CL = 50 pF, VCC = 4.5 V 8
Disable time, OE to Y tdis 32 ns CL = 50 pF, VCC = 6 V 8
Transition time, to Y tt 75 ns CL = 50 pF, VCC = 2 V 8
Transition time, to Y tt 15 ns CL = 50 pF, VCC = 4.5 V 8
Transition time, to Y tt 13 ns CL = 50 pF, VCC = 6 V 8
Propagation delay, A to Y tpd 210 ns CL = 150 pF, VCC = 2 V 8
Propagation delay, A to Y tpd 42 ns CL = 150 pF, VCC = 4.5 V 8
Propagation delay, A to Y tpd 35 ns CL = 150 pF, VCC = 6 V 8
Enable time, OE to Y ten 250 ns CL = 150 pF, VCC = 2 V 8
Enable time, OE to Y ten 50 ns CL = 150 pF, VCC = 4.5 V 8
Enable time, OE to Y ten 43 ns CL = 150 pF, VCC = 6 V 8
Transition time, to Y tt 265 ns CL = 150 pF, VCC = 2 V 9
Transition time, to Y tt 53 ns CL = 150 pF, VCC = 4.5 V 9
Transition time, to Y tt 45 ns CL = 150 pF, VCC = 6 V 9

CAD (KiCad official)

  • Symbol: SN74HC244APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hc244apwr-etched.step / sn74hc244apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc244apwr.step / sn74hc244apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 8bca6ed2074d65a9, retrieved 2026-10-28, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF