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SN74HC240N

Public Made by Adom

by adom

lingxingic Buffers, Drivers, Receivers, Transceivers, DIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HC240N

lingxingic · Buffers, Drivers, Receivers, Transceivers · DIP-20

SN74HC240N from lingxingic, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input for outputs 1Y0 to 1Y3, active LOW; a HIGH level forces these outputs into the high-impedance OFF-state.
2 1A0 input Data input for the 1Y0 buffer channel; the inputs include clamp diodes so current-limiting resistors can be used to interface to voltages above VCC.
3 2Y0 tri_state Inverting 3-state bus output of the 2Y0 channel, controlled by 2OE; high-impedance when 2OE is HIGH.
4 1A1 input Data input for the 1Y1 buffer channel; the inputs include clamp diodes so current-limiting resistors can be used to interface to voltages above VCC.
5 2Y1 tri_state Inverting 3-state bus output of the 2Y1 channel, controlled by 2OE; high-impedance when 2OE is HIGH.
6 1A2 input Data input for the 1Y2 buffer channel; the inputs include clamp diodes so current-limiting resistors can be used to interface to voltages above VCC.
7 2Y2 tri_state Inverting 3-state bus output of the 2Y2 channel, controlled by 2OE; high-impedance when 2OE is HIGH.
8 1A3 input Data input for the 1Y3 buffer channel; the inputs include clamp diodes so current-limiting resistors can be used to interface to voltages above VCC.
9 2Y3 tri_state Inverting 3-state bus output of the 2Y3 channel, controlled by 2OE; high-impedance when 2OE is HIGH.
10 GND power_in Ground reference (0 V) for all voltages in the datasheet.
11 2A3 input Data input for the 2Y3 buffer channel; the inputs include clamp diodes so current-limiting resistors can be used to interface to voltages above VCC.
12 1Y3 tri_state Inverting 3-state bus output of the 1Y3 channel, controlled by 1OE; high-impedance when 1OE is HIGH.
13 2A2 input Data input for the 2Y2 buffer channel; the inputs include clamp diodes so current-limiting resistors can be used to interface to voltages above VCC.
14 1Y2 tri_state Inverting 3-state bus output of the 1Y2 channel, controlled by 1OE; high-impedance when 1OE is HIGH.
15 2A1 input Data input for the 2Y1 buffer channel; the inputs include clamp diodes so current-limiting resistors can be used to interface to voltages above VCC.
16 1Y1 tri_state Inverting 3-state bus output of the 1Y1 channel, controlled by 1OE; high-impedance when 1OE is HIGH.
17 2A0 input Data input for the 2Y0 buffer channel; the inputs include clamp diodes so current-limiting resistors can be used to interface to voltages above VCC.
18 1Y0 tri_state Inverting 3-state bus output of the 1Y0 channel, controlled by 1OE; high-impedance when 1OE is HIGH.
19 2OE input Output enable input for outputs 2Y0 to 2Y3, active LOW; a HIGH level forces these outputs into the high-impedance OFF-state.
20 VCC power_in Supply voltage, recommended range 2.0 V to 6.0 V for SN74HC240 with absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 8
input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 8
output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 8
output current IO -35 35 mA -0.5V < VO < VCC+0.5V 8
supply current ICC 70 mA 8
ground current IGND -70 mA 8
storage temperature Tstg -65 150 ℃ 8
total power dissipation Ptot 500 mW 8
soldering temperature TL 245 ℃ 10s DIP 8
supply voltage VCC 2 5 6 V 8
input voltage VI 0 V 8
output voltage VO 0 V 8
input transition rise and fall rate Δt/ΔV 625 ns/V VCC=2.0V 8
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 8
input transition rise and fall rate Δt/ΔV 83 ns/V VCC=6.0V 8
ambient temperature Tamb -40 125 ℃ 8
HIGH-level input voltage VIH 1.5 1.2 V VCC=2.0V 9
HIGH-level input voltage VIH 3.15 2.4 V VCC=4.5V 9
HIGH-level input voltage VIH 4.2 3.2 V VCC=6.0V 9
LOW-level input voltage VIL 0.8 0.5 V VCC=2.0V 9
LOW-level input voltage VIL 2.1 1.35 V VCC=4.5V 9
LOW-level input voltage VIL 2.8 1.8 V VCC=6.0V 9
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO=-20uA; VCC=2.0V 9
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO=-20uA; VCC=4.5V 9
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO=-20uA; VCC=6.0V 9
HIGH-level output voltage VOH 3.98 4.32 V VI = VIH or VIL; IO=-6.0mA; VCC=4.5V 9
HIGH-level output voltage VOH 5.48 5.81 V VI = VIH or VIL; IO=-7.8mA; VCC=6.0V 9
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO=20uA; VCC=2.0V 9
LOW-level output voltage VOL 0.15 0.26 V VI = VIH or VIL; IO=6.0mA; VCC=4.5V 9
LOW-level output voltage VOL 0.16 0.26 V VI = VIH or VIL; IO=7.8mA; VCC=6.0V 9
input leakage current II -1 1 uA VI=VCC or GND; VCC=6.0V 9
OFF-state output current IOZ -1 1 uA VI=VIH or VIL; VCC=6.0V; VO=VCC or GND 9
supply current ICC 8 uA VI=VCC or GND; IO=0A; VCC=6.0V 9
nAn to nYn propagation delay tpd 30 100 ns VCC=2.0V; see Figure 5 12
nAn to nYn propagation delay tpd 11 20 ns VCC=4.5V; see Figure 5 12
nAn to nYn propagation delay tpd 9 17 ns VCC=6.0V; see Figure 5 12
nOE to nYn enable time ten 39 150 ns VCC=2.0V; see Figure 6 12
nOE to nYn enable time ten 14 30 ns VCC=4.5V; see Figure 6 12
nOE to nYn enable time ten 11 26 ns VCC=6.0V; see Figure 6 12
nOE to nYn disable time tdis 41 150 ns VCC=2.0V; see Figure 6 12
nOE to nYn disable time tdis 15 30 ns VCC=4.5V; see Figure 6 12
nOE to nYn disable time tdis 12 26 ns VCC=6.0V; see Figure 6 12
transition time tt 14 60 ns VCC=2.0V; see Figure 5 12
transition time tt 5 12 ns VCC=4.5V; see Figure 5 12
transition time tt 4 10 ns VCC=6.0V; see Figure 5 12
nAn to nYn propagation delay tpd 150 ns VCC=2.0V; see Figure 5 14
nAn to nYn propagation delay tpd 30 ns VCC=4.5V; see Figure 5 14
nAn to nYn propagation delay tpd 26 ns VCC=6.0V; see Figure 5 14
nOE to nYn enable time ten 225 ns VCC=2.0V; see Figure 6 14
nOE to nYn enable time ten 45 ns VCC=4.5V; see Figure 6 14
nOE to nYn enable time ten 38 ns VCC=6.0V; see Figure 6 14
nOE to nYn disable time tdis 225 ns VCC=2.0V; see Figure 6 14
nOE to nYn disable time tdis 45 ns VCC=4.5V; see Figure 6 14
nOE to nYn disable time tdis 38 ns VCC=6.0V; see Figure 6 14
transition time tt 90 ns VCC=2.0V; see Figure 5 14
transition time tt 18 ns VCC=4.5V; see Figure 5 14
transition time tt 15 ns VCC=6.0V; see Figure 5 14

CAD (KiCad official)

  • Symbol: SN74HC240N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: DIP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hc240n-etched.step / sn74hc240n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc240n.step / sn74hc240n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (20 pp, sha256 d324d392dc604725, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF