component
SN74HC20DR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC20DR
Texas Instruments · Logic Gates · SOIC-14
SN74HC20DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input Channel 1, Input A for 4-input NAND gate; accepts CMOS logic levels per recommended operating conditions |
| 2 | 1B | input | Input Channel 1, Input B for 4-input NAND gate; accepts CMOS logic levels per recommended operating conditions |
| 3 | NC | unconnected | Not internally connected |
| 4 | 1C | input | Input Channel 1, Input C for 4-input NAND gate; accepts CMOS logic levels per recommended operating conditions |
| 5 | 1D | input | Input Channel 1, Input D for 4-input NAND gate; accepts CMOS logic levels per recommended operating conditions |
| 6 | 1Y | output | Output Channel 1, Output Y of NAND gate performing Y = A●B●C●D; continuous output current ±25 mA maximum per absolute maximum ratings |
| 7 | GND | power_in | Ground; negative supply reference with continuous current rating of ±50 mA through GND per absolute maximum ratings |
| 8 | 2Y | output | Output Channel 2, Output Y of NAND gate performing Y = A●B●C●D; continuous output current ±25 mA maximum per absolute maximum ratings |
| 9 | 2A | input | Input Channel 2, Input A for 4-input NAND gate; accepts CMOS logic levels per recommended operating conditions |
| 10 | 2B | input | Input Channel 2, Input B for 4-input NAND gate; accepts CMOS logic levels per recommended operating conditions |
| 11 | NC | unconnected | Not internally connected |
| 12 | 2C | input | Input Channel 2, Input C for 4-input NAND gate; accepts CMOS logic levels per recommended operating conditions |
| 13 | 2D | input | Input Channel 2, Input D for 4-input NAND gate; accepts CMOS logic levels per recommended operating conditions |
| 14 | VCC | power_in | Positive Supply voltage; 2V to 6V nominal per recommended operating conditions with continuous current rating of ±50 mA through VCC per absolute maximum ratings |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74HC20DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hc20dr-etched.step/sn74hc20dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc20dr.step/sn74hc20dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
6879a7330d5c3dbe, retrieved 2026-09-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).