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SN74HC194N
Public Made by Adomby adom
lingxingic Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownSN74HC194N
lingxingic · Shift Registers · DIP-16
SN74HC194N from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Asynchronous master reset input, active LOW; a LOW forces Q0-Q3 to LOW regardless of CP. |
| 2 | DSR | input | Serial data input for shift-right operation. |
| 3 | D0 | input | Parallel data input, loaded into Q0 on a LOW-to-HIGH CP transition in parallel load mode (S1 = HIGH, S0 = HIGH). |
| 4 | D1 | input | Parallel data input, loaded into Q1 on a LOW-to-HIGH CP transition in parallel load mode (S1 = HIGH, S0 = HIGH). |
| 5 | D2 | input | Parallel data input, loaded into Q2 on a LOW-to-HIGH CP transition in parallel load mode (S1 = HIGH, S0 = HIGH). |
| 6 | D3 | input | Parallel data input, loaded into Q3 on a LOW-to-HIGH CP transition in parallel load mode (S1 = HIGH, S0 = HIGH). |
| 7 | DSL | input | Serial data input for shift-left operation. |
| 8 | GND | power_in | Ground (0 V) reference for the device. |
| 9 | S0 | input | Mode control input that, together with S1, selects hold, shift left, shift right, or parallel load on the CP edge. |
| 10 | S1 | input | Mode control input that, together with S0, selects hold, shift left, shift right, or parallel load on the CP edge. |
| 11 | CP | input | Clock input, triggered on the LOW-to-HIGH edge; S0/S1, data inputs and serial inputs are sampled on this edge. |
| 12 | Q3 | output | Parallel output, bit 3 of the register. |
| 13 | Q2 | output | Parallel output, bit 2 of the register. |
| 14 | Q1 | output | Parallel output, bit 1 of the register. |
| 15 | Q0 | output | Parallel output, bit 0 of the register. |
| 16 | VCC | power_in | Supply voltage; the SN74HC194 is specified for 2.0 V to 6.0 V (recommended operating range). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| HIGH-level input voltage | VIH | 1.5 | V | Tamb=-40℃ to +125℃; VCC=2.0V | 8 | ||
| HIGH-level input voltage | VIH | 3.15 | V | Tamb=-40℃ to +125℃; VCC=4.5V | 8 | ||
| HIGH-level input voltage | VIH | 4.2 | V | Tamb=-40℃ to +125℃; VCC=6.0V | 8 | ||
| LOW-level input voltage | VIL | 0.5 | V | Tamb=-40℃ to +125℃; VCC=2.0V | 8 | ||
| LOW-level input voltage | VIL | 1.35 | V | Tamb=-40℃ to +125℃; VCC=4.5V | 8 | ||
| LOW-level input voltage | VIL | 1.8 | V | Tamb=-40℃ to +125℃; VCC=6.0V | 8 | ||
| HIGH-level output voltage | VOH | 1.9 | V | Tamb=-40℃ to +125℃; VCC=2.0V; IO=-20uA | 8 | ||
| HIGH-level output voltage | VOH | 4.4 | V | Tamb=-40℃ to +125℃; VCC=4.5V; IO=-20uA | 8 | ||
| HIGH-level output voltage | VOH | 5.9 | V | Tamb=-40℃ to +125℃; VCC=6.0V; IO=-20uA | 8 | ||
| HIGH-level output voltage | VOH | 3.7 | V | Tamb=-40℃ to +125℃; VCC=4.5V; IO=-4.0mA | 8 | ||
| HIGH-level output voltage | VOH | 5.2 | V | Tamb=-40℃ to +125℃; VCC=6.0V; IO=-5.2mA | 8 | ||
| LOW-level output voltage | VOL | 0.1 | V | Tamb=-40℃ to +125℃; VCC=2.0V; IO=20uA | 8 | ||
| LOW-level output voltage | VOL | 0.4 | V | Tamb=-40℃ to +125℃; VCC=4.5V; IO=4.0mA | 8 | ||
| input leakage current | II | -1 | 1 | uA | Tamb=-40℃ to +125℃; VCC=6.0V; VI=VCC or GND | 8 | |
| supply current | ICC | 160 | uA | Tamb=-40℃ to +125℃; VCC=6.0V; VI=VCC or GND; IO=0A | 8 | ||
| CP to Qn propagation delay | tPLH, tPHL | 220 | ns | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 | 11 | ||
| CP to Qn propagation delay | tPLH, tPHL | 44 | ns | Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF | 11 | ||
| CP to Qn propagation delay | tPLH, tPHL | 38 | ns | Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF | 11 | ||
| MR to Qn propagation delay | tPHL | 210 | ns | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 5 | 11 | ||
| MR to Qn propagation delay | tPHL | 42 | ns | Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF | 11 | ||
| MR to Qn propagation delay | tPHL | 36 | ns | Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF | 11 | ||
| clock pulse width | tW | 120 | ns | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 | 11 | ||
| clock pulse width | tW | 24 | ns | Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF | 11 | ||
| clock pulse width | tW | 20 | ns | Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF | 11 | ||
| master reset pulse width | tW | 120 | ns | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 5 | 11 | ||
| master reset pulse width | tW | 24 | ns | Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF | 11 | ||
| master reset pulse width | tW | 20 | ns | Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF | 11 | ||
| Dn to CP set-up time | tsu | 105 | ns | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 6 | 11 | ||
| Dn to CP set-up time | tsu | 21 | ns | Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF | 11 | ||
| Dn to CP set-up time | tsu | 18 | ns | Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF | 11 | ||
| S0, S1 to CP set-up time | tsu | 120 | ns | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 7 | 11 | ||
| S0, S1 to CP set-up time | tsu | 24 | ns | Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF | 11 | ||
| S0, S1 to CP set-up time | tsu | 20 | ns | Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF | 11 | ||
| DSR, DSL to CP set-up time | tsu | 105 | ns | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 6 | 11 | ||
| DSR, DSL to CP set-up time | tsu | 21 | ns | Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF | 11 | ||
| DSR, DSL to CP set-up time | tsu | 18 | ns | Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF | 11 | ||
| Dn to CP hold time | th | 0 | ns | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 6 | 11 | ||
| S0, S1 to CP hold time | th | 0 | ns | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 7 | 11 | ||
| maximum clock pulse frequency | fmax | 4 | MHz | Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 | 11 | ||
| maximum clock pulse frequency | fmax | 20 | MHz | Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF | 11 | ||
| maximum clock pulse frequency | fmax | 24 | MHz | Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF | 11 | ||
| supply voltage | VCC | 2 | 5 | 6 | V | 7 | |
| input voltage | VI | 0 | V | 7 | |||
| output voltage | VO | 0 | V | 7 | |||
| ambient temperature | Tamb | -40 | 125 | ℃ | 7 | ||
| supply voltage | VCC | -0.5 | 7 | V | 7 | ||
| supply current | ICC | 50 | mA | 7 | |||
| ground current | IGND | -50 | mA | 7 | |||
| input clamping current | IIK | -20 | 20 | mA | VI<-0.5V or VI>VCC+0.5V | 7 | |
| output clamping current | IOK | -20 | 20 | mA | VO<-0.5V or VO>VCC+0.5V | 7 | |
| output current | IO | -25 | 25 | mA | -0.5V<VO<VCC+0.5V | 7 | |
| storage temperature | Tstg | -65 | 150 | ℃ | 7 | ||
| soldering temperature | TL | 245 | ℃ | 10s, DIP | 7 |
CAD (KiCad official)
- Symbol:
SN74HC194N - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hc194n-etched.step/sn74hc194n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc194n.step/sn74hc194n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (19 pp, sha256
b46d910d51e2788b, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).