component
SN74HC194 Universal Shift Register
Public Made by Adomby adom
4-bit bidirectional universal shift register with parallel load and shift-left/right control.
main
Ray
sn74hc194: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
ae636a0
1mo ago
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{
"schema_version": 1,
"type": "component",
"slug": "sn74hc194",
"title": "SN74HC194 Universal Shift Register",
"brief": "4-bit bidirectional universal shift register with parallel load and shift-left/right control.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"logic",
"shift-register",
"bidirectional",
"universal",
"74hc",
"ti",
"soic-16"
],
"component": {
"mpn": "SN74HC194",
"manufacturer": "Texas Instruments",
"package": "SOIC-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Shift Register",
"datasheet": "https://www.ti.com/lit/ds/symlink/cd74hc194.pdf",
"parts": {
"symbol": "sn74hc194.kicad_sym",
"footprint": "sn74hc194.kicad_mod",
"model_3d": "sn74hc194-etched.glb",
"model_3d_plain": "sn74hc194.glb",
"lbr": "sn74hc194.lbr",
"model_3d_step": "sn74hc194-etched.step",
"model_3d_step_plain": "sn74hc194.step"
},
"distributor_links": {},
"pins": [
{
"number": "1",
"name": "MR",
"type": "input",
"description": "Asynchronous Master Reset, active-low. When driven low, all four internal flip-flops are cleared and Q0-Q3 are forced to logic Low regardless of the clock. Minimum MR pulse width is 16ns at VCC=4.5V."
},
{
"number": "2",
"name": "DSR",
"type": "input",
"description": "Serial data input for shift-right mode. The logic level on DSR is clocked into Q0 on the rising edge of CP when S1=Low, S0=High."
},
{
"number": "3",
"name": "D0",
"type": "input",
"description": "Parallel data input D0. Loaded into flip-flop Q0 on the rising edge of CP when S0=High and S1=High (parallel load mode)."
},
{
"number": "4",
"name": "D1",
"type": "input",
"description": "Parallel data input D1. Loaded into flip-flop Q1 on the rising edge of CP when S0=High and S1=High (parallel load mode)."
},
{
"number": "5",
"name": "D2",
"type": "input",
"description": "Parallel data input D2. Loaded into flip-flop Q2 on the rising edge of CP when S0=High and S1=High (parallel load mode)."
},
{
"number": "6",
"name": "D3",
"type": "input",
"description": "Parallel data input D3. Loaded into flip-flop Q3 on the rising edge of CP when S0=High and S1=High (parallel load mode)."
},
{
"number": "7",
"name": "DSL",
"type": "input",
"description": "Serial data input for shift-left mode. The logic level on DSL is clocked into Q3 on the rising edge of CP when S1=High, S0=Low."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground reference (0V) for the device."
},
{
"number": "9",
"name": "S0",
"type": "input",
"description": "Mode select input S0. Combined with S1 selects one of four operating modes: hold (S1=L,S0=L), shift-right (S1=L,S0=H), shift-left (S1=H,S0=L), parallel load (S1=H,S0=H)."
},
{
"number": "10",
"name": "S1",
"type": "input",
"description": "Mode select input S1. See S0 for the mode encoding table."
},
{
"number": "11",
"name": "CP",
"type": "input",
"description": "Clock input. All synchronous operations (shift-right, shift-left, parallel-load, hold) occur on the rising (Low-to-High) edge of CP. Typical fMAX = 60MHz at VCC=5V, CL=15pF."
},
{
"number": "12",
"name": "Q3",
"type": "output",
"description": "Parallel output Q3, the MSB of the shift register. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low."
},
{
"number": "13",
"name": "Q2",
"type": "output",
"description": "Parallel output Q2. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low."
},
{
"number": "14",
"name": "Q1",
"type": "output",
"description": "Parallel output Q1. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low."
},
{
"number": "15",
"name": "Q0",
"type": "output",
"description": "Parallel output Q0, the LSB of the shift register. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Positive supply voltage. 2V to 6V for HC types, 4.5V to 5.5V for HCT types. Bypass with a 100nF ceramic capacitor close to the pin."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/cd74hc194.pdf",
"pages": 19,
"sha256": "209a444fe7a9beeb",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"logic": {
"family_id": "74HC194",
"logic_family": "74HC",
"function_code": "194",
"function_class": null,
"function_name": null,
"manufacturer": "Texas Instruments",
"is_specialty": false
},
"models_3d": [
{
"file": "sn74hc194.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
9.9,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "sn74hc194-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
9.9,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "76840662dedb35d96c9e4972eac7b16d0cfb57784fb5a5b3a380d10cb9c1c125",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Type": "4-bit bidirectional universal shift register",
"Logic family": "74HC (CMOS)",
"Modes": "Shift left, shift right, parallel load, hold",
"Clear": "Active-low, asynchronous",
"Supply voltage": "2 V to 6 V",
"Max clock": "50 MHz typ at 5 V",
"Operating temperature": "-40 C to 85 C"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"universal shift register",
"bidirectional shift register",
"parallel load shift",
"shift left right"
],
"discovery_pitch": "A 4-bit register that shifts left, shifts right, parallel-loads, or holds under two mode pins.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"sn74hc194.kicad_sym",
"sn74hc194.kicad_mod",
"sn74hc194.glb",
"sn74hc194.lbr",
"docs/hero.png",
"docs/sn74hc194-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"sn74hc194-etched.step"
],
"variants": [
{
"mpn": "SN74HC194E",
"kind": "unknown"
},
{
"mpn": "SN74HC194M",
"kind": "unknown"
},
{
"mpn": "SN74HC194MT",
"kind": "unknown"
},
{
"mpn": "SN74HC194M96",
"kind": "unknown"
},
{
"mpn": "SN74HC194NSR",
"kind": "unknown"
},
{
"mpn": "SN74HC194PW",
"kind": "unknown"
},
{
"mpn": "SN74HC194PWR",
"kind": "unknown"
},
{
"mpn": "SN74HC194PWT",
"kind": "unknown"
},
{
"mpn": "SN74HC194F3A",
"kind": "unknown"
}
]
}