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SN74HC175PWR

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Texas Instruments Flip Flops, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74HC175PWR

Texas Instruments · Flip Flops · TSSOP-16

SN74HC175PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low direct clear input that forces all Q outputs low and all Q-bar outputs high when low.
2 1Q output True output of flip-flop 1.
3 1Q̅ output Complementary output of flip-flop 1.
4 1D input Data input of flip-flop 1, transferred to the outputs on the positive clock edge.
5 2D input Data input of flip-flop 2, transferred to the outputs on the positive clock edge.
6 2Q̅ output Complementary output of flip-flop 2.
7 2Q output True output of flip-flop 2.
8 GND power_in Ground pin.
9 CLK input Common positive-edge clock input for all four flip-flops.
10 3Q output True output of flip-flop 3.
11 3Q̅ output Complementary output of flip-flop 3.
12 3D input Data input of flip-flop 3, transferred to the outputs on the positive clock edge.
13 4D input Data input of flip-flop 4, transferred to the outputs on the positive clock edge.
14 4Q̅ output Complementary output of flip-flop 4.
15 4Q output True output of flip-flop 4.
16 VCC power_in Supply voltage pin, 2 V to 6 V recommended, with a 0.1-μF bypass capacitor recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (VCC) VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage VCC 2 5 6 V SN74HC175 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input transition rise/fall time tt 1000 ns VCC = 2 V 4
Input transition rise/fall time tt 500 ns VCC = 4.5 V 4
Input transition rise/fall time tt 400 ns VCC = 6 V 4
Operating free-air temperature TA -40 85 °C SN74HC175 4
High-level output voltage VOH 1.9 V VI = VIH or VIL, IOH = −20 μA, VCC = 2 V 5
High-level output voltage VOH 4.4 V VI = VIH or VIL, IOH = −20 μA, VCC = 4.5 V 5
High-level output voltage VOH 5.9 V VI = VIH or VIL, IOH = −20 μA, VCC = 6 V 5
High-level output voltage VOH 3.84 V VI = VIH or VIL, IOH = −4 mA, VCC = 4.5 V 5
High-level output voltage VOH 5.34 V VI = VIH or VIL, IOH = −5.2 mA, VCC = 6 V 5
Low-level output voltage VOL 0.1 V VI = VIH or VIL, IOL = 20 μA, VCC = 2 V 5
Low-level output voltage VOL 0.33 V VI = VIH or VIL, IOL = 4 mA, VCC = 4.5 V 5
Input leakage current II -1000 1000 nA VI = VCC or 0, VCC = 6 V 5
Supply current ICC 80 μA VI = VCC or 0, IO = 0, VCC = 6 V 5
Input capacitance Ci 10 pF VCC = 2 V to 6 V 5
Clock frequency fclock 5 MHz VCC = 2 V 5
Clock frequency fclock 25 MHz VCC = 4.5 V 5
Clock frequency fclock 29 MHz VCC = 6 V 5
Pulse duration, CLR low tw 100 ns VCC = 2 V 5
Pulse duration, CLR low tw 20 ns VCC = 4.5 V 5
Pulse duration, CLR low tw 17 ns VCC = 6 V 5
Pulse duration, CLK high or low tw 100 ns VCC = 2 V 5
Pulse duration, CLK high or low tw 20 ns VCC = 4.5 V 5
Pulse duration, CLK high or low tw 17 ns VCC = 6 V 5
Setup time before CLK↑, data tsu 125 ns VCC = 2 V 5
Setup time before CLK↑, data tsu 25 ns VCC = 4.5 V 5
Setup time before CLK↑, data tsu 21 ns VCC = 6 V 5
Setup time before CLK↑, CLR inactive tsu 125 ns VCC = 2 V 5
Setup time before CLK↑, CLR inactive tsu 25 ns VCC = 4.5 V 5
Setup time before CLK↑, CLR inactive tsu 21 ns VCC = 6 V 5
Maximum clock frequency fmax 5 MHz VCC = 2 V, CL = 50 pF 6
Maximum clock frequency fmax 25 MHz VCC = 4.5 V, CL = 50 pF 6
Maximum clock frequency fmax 29 MHz VCC = 6 V, CL = 50 pF 6
Propagation delay, CLR to any output tpd 190 ns VCC = 2 V, CL = 50 pF 6
Propagation delay, CLR to any output tpd 38 ns VCC = 4.5 V, CL = 50 pF 6
Propagation delay, CLR to any output tpd 32 ns VCC = 6 V, CL = 50 pF 6
Propagation delay, CLK to any output tpd 190 ns VCC = 2 V, CL = 50 pF 6
Propagation delay, CLK to any output tpd 38 ns VCC = 4.5 V, CL = 50 pF 6
Propagation delay, CLK to any output tpd 32 ns VCC = 6 V, CL = 50 pF 6
Output transition time tt 90 ns VCC = 2 V, CL = 50 pF 6
Output transition time tt 19 ns VCC = 4.5 V, CL = 50 pF 6
Output transition time tt 16 ns VCC = 6 V, CL = 50 pF 6
Junction-to-ambient thermal resistance (PW, TSSOP-16) RθJA 137.5 °C/W PW (TSSOP) 16-pin package 4

CAD (KiCad official)

  • Symbol: SN74HC175PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc175pwr-etched.step / sn74hc175pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc175pwr.step / sn74hc175pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 ae5df0024a2097a5, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF