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SN74HC175DR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC175DR
Texas Instruments · Flip Flops · SOIC-16
SN74HC175DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Active-low asynchronous direct clear input shared by all four flip-flops; when LOW, forces all Q outputs LOW and all Q̄ outputs HIGH regardless of CLK or D; setup time before CLK↑ ≥ 20 ns at VCC = 4.5 V. |
| 2 | 1Q | output | Non-inverting output of flip-flop 1; captures the state of 1D on the positive-going edge of CLK; IOH = −4 mA at VCC = 4.5 V, tpd = 30 ns max at VCC = 4.5 V. |
| 3 | 1Q_N | output | Complementary (inverting) output of flip-flop 1; always the logical inverse of 1Q; IOL = 4 mA at VCC = 4.5 V. |
| 4 | 1D | input | Data input of flip-flop 1; state is transferred to 1Q on the positive-going CLK edge; setup time tsu = 20 ns min at VCC = 4.5 V, hold time th = 0 ns. |
| 5 | 2D | input | Data input of flip-flop 2; state is transferred to 2Q on the positive-going CLK edge; setup time tsu = 20 ns min at VCC = 4.5 V, hold time th = 0 ns. |
| 6 | 2Q_N | output | Complementary (inverting) output of flip-flop 2; always the logical inverse of 2Q; IOL = 4 mA at VCC = 4.5 V. |
| 7 | 2Q | output | Non-inverting output of flip-flop 2; captures the state of 2D on the positive-going edge of CLK; IOH = −4 mA at VCC = 4.5 V, tpd = 30 ns max at VCC = 4.5 V. |
| 8 | GND | power_in | Ground reference; continuous current through GND pin limited to ±50 mA. |
| 9 | CLK | input | Common positive-edge-triggered clock input for all four flip-flops; minimum pulse width tw = 16 ns at VCC = 4.5 V; maximum clock frequency fmax = 25 MHz (SN74HC175) at VCC = 4.5 V. |
| 10 | 3Q | output | Non-inverting output of flip-flop 3; captures the state of 3D on the positive-going edge of CLK; IOH = −4 mA at VCC = 4.5 V, tpd = 30 ns max at VCC = 4.5 V. |
| 11 | 3Q_N | output | Complementary (inverting) output of flip-flop 3; always the logical inverse of 3Q; IOL = 4 mA at VCC = 4.5 V. |
| 12 | 3D | input | Data input of flip-flop 3; state is transferred to 3Q on the positive-going CLK edge; setup time tsu = 20 ns min at VCC = 4.5 V, hold time th = 0 ns. |
| 13 | 4D | input | Data input of flip-flop 4; state is transferred to 4Q on the positive-going CLK edge; setup time tsu = 20 ns min at VCC = 4.5 V, hold time th = 0 ns. |
| 14 | 4Q_N | output | Complementary (inverting) output of flip-flop 4; always the logical inverse of 4Q; IOL = 4 mA at VCC = 4.5 V. |
| 15 | 4Q | output | Non-inverting output of flip-flop 4; captures the state of 4D on the positive-going edge of CLK; IOH = −4 mA at VCC = 4.5 V, tpd = 30 ns max at VCC = 4.5 V. |
| 16 | VCC | power_in | Positive supply voltage; recommended operating range 2 V to 6 V; bypass with 0.1 µF capacitor placed as close to the pin as possible; ICC max = 80 µA at VCC = 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74HC175DR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hc175dr-etched.step/sn74hc175dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc175dr.step/sn74hc175dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
3ebf84d0694c4b5d, retrieved 2026-09-29, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).