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SN74HC174DR

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Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74HC174DR

Texas Instruments · Flip Flops · SOIC-16

SN74HC174DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low asynchronous clear input; when low it forces all six flip-flop outputs (Q) low regardless of CLK or D.
2 1Q output Output of flip-flop 1, reflecting the state of D1 latched on the last CLK positive edge (or forced low by CLR).
3 1D input Data input to flip-flop 1; its logic level is transferred to 1Q on the positive-going edge of CLK when CLR is high.
4 2D input Data input to flip-flop 2; its logic level is transferred to 2Q on the positive-going edge of CLK when CLR is high.
5 2Q output Output of flip-flop 2, reflecting the state of D2 latched on the last CLK positive edge (or forced low by CLR).
6 3D input Data input to flip-flop 3; its logic level is transferred to 3Q on the positive-going edge of CLK when CLR is high.
7 3Q output Output of flip-flop 3, reflecting the state of D3 latched on the last CLK positive edge (or forced low by CLR).
8 GND power_in Ground reference (0 V) supply pin for the device.
9 CLK input Common clock input shared by all six flip-flops; data at D inputs meeting setup time is transferred to Q outputs on its positive-going edge.
10 4Q output Output of flip-flop 4, reflecting the state of D4 latched on the last CLK positive edge (or forced low by CLR).
11 4D input Data input to flip-flop 4; its logic level is transferred to 4Q on the positive-going edge of CLK when CLR is high.
12 5Q output Output of flip-flop 5, reflecting the state of D5 latched on the last CLK positive edge (or forced low by CLR).
13 5D input Data input to flip-flop 5; its logic level is transferred to 5Q on the positive-going edge of CLK when CLR is high.
14 6D input Data input to flip-flop 6; its logic level is transferred to 6Q on the positive-going edge of CLK when CLR is high.
15 6Q output Output of flip-flop 6, reflecting the state of D6 latched on the last CLK positive edge (or forced low by CLR).
16 VCC power_in Positive supply voltage pin, recommended operating range 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74HC174DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc174dr-etched.step / sn74hc174dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc174dr.step / sn74hc174dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 9b979c6ba2b4b122, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-5 (text+vision), consensus claude-opus-4-8 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF