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SN74HC166DBR

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Texas Instruments Shift Registers, SSOP-16-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HC166DBR

Texas Instruments · Shift Registers · SSOP-16-208mil

SN74HC166DBR from Texas Instruments, in a SSOP-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SER input Serial data input; data on SER is shifted into the first register on each clock pulse while SH/LD is high.
2 A input Parallel data input A; loaded synchronously into its internal register on the next clock pulse while SH/LD is low.
3 B input Parallel data input B; loaded synchronously into its internal register on the next clock pulse while SH/LD is low.
4 C input Parallel data input C; loaded synchronously into its internal register on the next clock pulse while SH/LD is low.
5 D input Parallel data input D; loaded synchronously into its internal register on the next clock pulse while SH/LD is low.
6 CLK INH input Clock inhibit input; holding it high inhibits the clock, and it should only be changed to high while CLK is high.
7 CLK input Clock input, triggered on the rising edge; holding it high inhibits the clock, and it can serve as a clock enable together with CLK INH.
8 GND power_in Ground reference for the device.
9 CLR input Active-low clear input that overrides all other inputs, including CLK, and resets all internal flip-flops to zero.
10 E input Parallel data input E; loaded synchronously into its internal register on the next clock pulse while SH/LD is low.
11 F input Parallel data input F; loaded synchronously into its internal register on the next clock pulse while SH/LD is low.
12 G input Parallel data input G; loaded synchronously into its internal register on the next clock pulse while SH/LD is low.
13 QH output Serial data output from the last shift register stage, driven high or low according to the register contents during shifting.
14 H input Parallel data input H; loaded synchronously into its internal register on the next clock pulse while SH/LD is low.
15 SH/LD input Mode select input: high enables serial shifting from SER, low selects parallel load of inputs A to H on the next clock pulse.
16 VCC power_in Positive supply voltage, specified for 2 V to 6 V in the recommended operating conditions, with a 0.1 µF bypass capacitor recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-16-208mil
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74HC166DBR
  • Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-16-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74hc166dbr-etched.step / sn74hc166dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc166dbr.step / sn74hc166dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 406bac53e0e938e2, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF