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SN74HC165QPWRQ1

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Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74hc165qpwrq1factory-2.0.0extractor-text

Verified SN74HC165QPWRQ1

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN74HC165QPWRQ1 · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 17-page datasheet
  • ✓distributor: lcsc C2877051, digikey 296-49893-2-ND, mouser 595-SN74HC165QPWRQ1
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-dge4e215/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn74hc165qpwrq1.kicad_sym✓ sn74hc165qpwrq1.kicad_mod✓ sn74hc165qpwrq1.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3h ago
viewers sn74hc165qpwrq1: viewers · Ray 3h ago
package.json Publish 0.1.0 · Ray 3h ago
page.json Set visibility: public · Ray 3h ago
README.md Publish 0.1.0 · Ray 3h ago
sn74hc165qpwrq1-etched.glb Publish 0.1.0 · Ray 3h ago
sn74hc165qpwrq1-etched.step sn74hc165qpwrq1: factory component page (tier=mfr) · Ray 3h ago
sn74hc165qpwrq1-hero.glb sn74hc165qpwrq1: hero GLB from the etched model (keeps the MPN mark) · Ray 3h ago
sn74hc165qpwrq1-hero.overlay.json Publish 0.1.0 · Ray 3h ago
sn74hc165qpwrq1.glb Publish 0.1.0 · Ray 3h ago
sn74hc165qpwrq1.kicad_mod Publish 0.1.0 · Ray 3h ago
sn74hc165qpwrq1.kicad_sym Publish 0.1.0 · Ray 3h ago
sn74hc165qpwrq1.lbr Publish 0.1.0 · Ray 3h ago
sn74hc165qpwrq1.step Publish 0.1.0 · Ray 3h ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 2h ago

SN74HC165QPWRQ1

Texas Instruments · Shift Registers · TSSOP-16

SN74HC165QPWRQ1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SH/LD input Shift/load input: a low level enables the parallel inputs A-H to load, and a high level holds parallel loading inhibited.
2 CLK input Clock input: a low-to-high transition clocks the register while SH/LD is high and CLK INH is low.
3 E input Direct parallel data input for stage E, enabled when SH/LD is low.
4 F input Direct parallel data input for stage F, enabled when SH/LD is low.
5 G input Direct parallel data input for stage G, enabled when SH/LD is low.
6 H input Direct parallel data input for stage H, enabled when SH/LD is low.
7 QH output Serial output of the shift register; data shifts toward this output on each clock.
8 GND power_in Ground reference pin for the device.
9 QH output Complementary serial output of the shift register, the inverse of QH.
10 SER input Serial data input; the level present here is shifted into the first register stage on each clock.
11 A input Direct parallel data input for stage A, enabled when SH/LD is low.
12 B input Direct parallel data input for stage B, enabled when SH/LD is low.
13 C input Direct parallel data input for stage C, enabled when SH/LD is low.
14 D input Direct parallel data input for stage D, enabled when SH/LD is low.
15 CLK INH input Clock inhibit input; it should be changed to high only while CLK is high, and a low level allows clocking.
16 VCC power_in Supply voltage pin; the recommended operating range is 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 5 6 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input transition rise/fall time t/v 1000 ns VCC = 2 V 4
Input transition rise/fall time t/v 500 ns VCC = 4.5 V 4
Input transition rise/fall time t/v 400 ns VCC = 6 V 4
Operating free-air temperature TA -40 125 °C 4
Supply voltage range VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Package thermal impedance PW package θJA 108 °C/W PW package, JESD 51-7 4
Package thermal impedance D package θJA 73 °C/W D package, JESD 51-7 4
Storage temperature range Tstg -65 150 °C 4
High-level output voltage VOH 1.9 1.998 V IOH = −20 µA, VCC = 2 V 5
High-level output voltage VOH 4.4 4.499 V IOH = −20 µA, VCC = 4.5 V 5
High-level output voltage VOH 5.9 5.999 V IOH = −20 µA, VCC = 6 V 5
High-level output voltage VOH 3.7 4.3 V IOH = −4 mA, VCC = 4.5 V 5
High-level output voltage VOH 5.2 5.8 V IOH = −5.2 mA, VCC = 6 V 5
Low-level output voltage VOL 0.002 0.1 V IOL = 20 µA, VCC = 2 V 5
Low-level output voltage VOL 0.001 0.1 V IOL = 20 µA, VCC = 4.5 V 5
Low-level output voltage VOL 0.17 0.4 V IOL = 4 mA, VCC = 4.5 V 5
Low-level output voltage VOL 0.15 0.4 V IOL = 5.2 mA, VCC = 6 V 5
Input leakage current II -1000 0.1 1000 nA VI = VCC or 0, VCC = 6 V 5
Supply current ICC 8 160 µA VI = VCC or 0, IO = 0, VCC = 6 V 5
Input capacitance Ci 3 10 pF VCC = 2 V to 6 V 5
Clock frequency fclock 4.2 MHz VCC = 2 V, over operating range 6
Clock frequency fclock 21 MHz VCC = 4.5 V, over operating range 6
Clock frequency fclock 25 MHz VCC = 6 V, over operating range 6
Pulse duration SH/LD low tw 120 ns SH/LD low, VCC = 2 V 6
Pulse duration SH/LD low tw 24 ns SH/LD low, VCC = 4.5 V 6
Pulse duration SH/LD low tw 20 ns SH/LD low, VCC = 6 V 6
Pulse duration CLK high or low tw 120 ns CLK high or low, VCC = 2 V 6
Pulse duration CLK high or low tw 24 ns CLK high or low, VCC = 4.5 V 6
Pulse duration CLK high or low tw 20 ns CLK high or low, VCC = 6 V 6
Setup time SH/LD high before CLK high tsu 120 ns VCC = 2 V 6
Setup time SH/LD high before CLK high tsu 24 ns VCC = 4.5 V 6
Setup time SH/LD high before CLK high tsu 20 ns VCC = 6 V 6
Setup time SER before CLK↑ tsu 60 ns VCC = 2 V 6
Setup time SER before CLK↑ tsu 12 ns VCC = 4.5 V 6
Setup time SER before CLK↑ tsu 10 ns VCC = 6 V 6
Setup time CLK INH low before CLK↑ tsu 150 ns VCC = 2 V 6
Setup time CLK INH low before CLK↑ tsu 30 ns VCC = 4.5 V 6
Setup time CLK INH low before CLK↑ tsu 25 ns VCC = 6 V 6
Setup time CLK INH high before CLK↑ tsu 60 ns VCC = 2 V 6
Setup time CLK INH high before CLK↑ tsu 12 ns VCC = 4.5 V 6
Setup time CLK INH high before CLK↑ tsu 10 ns VCC = 6 V 6
Setup time data before SH/LD↓ tsu 150 ns VCC = 2 V 6
Setup time data before SH/LD↓ tsu 30 ns VCC = 4.5 V 6
Setup time data before SH/LD↓ tsu 26 ns VCC = 6 V 6
Hold time SER data after CLK↑ th 5 ns VCC = 2 V 6
Maximum clock frequency fmax 4.2 MHz VCC = 2 V, over operating range 7
Maximum clock frequency fmax 21 MHz VCC = 4.5 V, over operating range 7
Maximum clock frequency fmax 25 MHz VCC = 6 V, over operating range 7
Propagation delay SH/LD to QH or QH̄ tpd 225 ns VCC = 2 V, CL = 50 pF 7
Propagation delay SH/LD to QH or QH̄ tpd 45 ns VCC = 4.5 V, CL = 50 pF 7
Propagation delay SH/LD to QH or QH̄ tpd 38 ns VCC = 6 V, CL = 50 pF 7
Propagation delay CLK to QH or QH̄ tpd 225 ns VCC = 2 V, CL = 50 pF 7
Propagation delay CLK to QH or QH̄ tpd 45 ns VCC = 4.5 V, CL = 50 pF 7
Propagation delay CLK to QH or QH̄ tpd 38 ns VCC = 6 V, CL = 50 pF 7
Propagation delay H to QH or QH̄ tpd 225 ns VCC = 2 V, CL = 50 pF 7
Propagation delay H to QH or QH̄ tpd 45 ns VCC = 4.5 V, CL = 50 pF 7
Propagation delay H to QH or QH̄ tpd 38 ns VCC = 6 V, CL = 50 pF 7
Output transition time tt 110 ns VCC = 2 V, CL = 50 pF 7
Output transition time tt 22 ns VCC = 4.5 V, CL = 50 pF 7
Output transition time tt 19 ns VCC = 6 V, CL = 50 pF 7
Power dissipation capacitance Cpd 75 pF No load, TA = 25°C 7

CAD (KiCad official)

  • Symbol: SN74HC165QPWRQ1
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc165qpwrq1-etched.step / sn74hc165qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc165qpwrq1.step / sn74hc165qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 48c57034abfdb27f, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF