component

SN74HC165PWR

Public Made by Adom

by adom

Texas Instruments Shift Registers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentlogicsn74hc165pwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74HC165PWR

Texas Instruments · Shift Registers · TSSOP-16

SN74HC165PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SH/LD input Shift/Load control input; when high enables shift mode on clock edges, when low enables parallel data loading from inputs A-H.
2 CLK input Clock input; rising edge shifts data toward QH when SH/LD is high and CLK INH is low.
3 E input Parallel data input for stage 4; loaded into shift register when SH/LD is low.
4 F input Parallel data input for stage 5; loaded into shift register when SH/LD is low.
5 G input Parallel data input for stage 6; loaded into shift register when SH/LD is low.
6 H input Parallel data input for stage 7; loaded into shift register when SH/LD is low.
7 QH output Complementary serial output; inverted version of the serial data from stage 7.
8 GND power_in Ground; system reference voltage (0 V).
9 QH output Serial output; non-inverted data from the 8th stage of the shift register.
10 SER input Serial input; data bit enters the first stage on rising clock edges when in shift mode.
11 A input Parallel data input for stage 0; loaded into shift register when SH/LD is low.
12 B input Parallel data input for stage 1; loaded into shift register when SH/LD is low.
13 C input Parallel data input for stage 2; loaded into shift register when SH/LD is low.
14 D input Parallel data input for stage 3; loaded into shift register when SH/LD is low.
15 CLK INH input Clock inhibit input; when high, disables clocking regardless of CLK state, inhibiting shift operation.
16 VCC power_in Positive supply voltage; operating range 2 V to 6 V per Recommended Operating Conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74HC165PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc165pwr-etched.step / sn74hc165pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc165pwr.step / sn74hc165pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 517390062d4006fc, retrieved 2026-09-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF