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SN74HC165APWR

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Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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SN74HC165APWR

Texas Instruments · Shift Registers · TSSOP-16

SN74HC165APWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SH/LD input Shift/Load select input; HIGH enables serial shifting on CLK rising edge; LOW enables parallel load from inputs A-H independent of CLK and CLK INH; VIH min 3.15 V at VCC = 4.5 V.
2 CLK input Clock input; data shifts toward QH on low-to-high transition when SH/LD is HIGH and CLK INH is LOW; max frequency 31 MHz at VCC = 4.5 V, 25°C; function interchangeable with CLK INH.
3 E input Parallel data input E; loaded into 5th shift-register stage when SH/LD is LOW; setup time 20 ns before SH/LD↓ at VCC = 4.5 V.
4 F input Parallel data input F; loaded into 6th shift-register stage when SH/LD is LOW; setup time 20 ns before SH/LD↓ at VCC = 4.5 V.
5 G input Parallel data input G; loaded into 7th shift-register stage when SH/LD is LOW; setup time 20 ns before SH/LD↓ at VCC = 4.5 V.
6 H input Parallel data input H; loaded into 8th (final) shift-register stage when SH/LD is LOW; setup time 20 ns before SH/LD↓ at VCC = 4.5 V.
7 ~QH output Complementary serial output; inverted logic level of QH; VOH min 3.98 V at IOH = −4 mA, VCC = 4.5 V; tpd max 30 ns at VCC = 4.5 V, 25°C.
8 GND power_in Ground reference (0 V); continuous current through GND pin ±50 mA absolute maximum.
9 QH output Serial data output from last shift-register stage; VOH min 3.98 V at IOH = −4 mA, VCC = 4.5 V; tpd typical 15 ns at VCC = 4.5 V, 25°C.
10 SER input Serial data input; clocked into the first register stage on CLK↑ when SH/LD is HIGH; setup time 8 ns before CLK↑ at VCC = 4.5 V, 25°C.
11 A input Parallel data input A; loaded into 1st shift-register stage when SH/LD is LOW; hold time 5 ns after SH/LD↓ at VCC = 4.5 V.
12 B input Parallel data input B; loaded into 2nd shift-register stage when SH/LD is LOW; hold time 5 ns after SH/LD↓ at VCC = 4.5 V.
13 C input Parallel data input C; loaded into 3rd shift-register stage when SH/LD is LOW; hold time 5 ns after SH/LD↓ at VCC = 4.5 V.
14 D input Parallel data input D; loaded into 4th shift-register stage when SH/LD is LOW; hold time 5 ns after SH/LD↓ at VCC = 4.5 V.
15 CLK INH input Clock inhibit input; HIGH holds all outputs unchanged regardless of CLK state; interchangeable with CLK; setup time 20 ns before CLK↑ at VCC = 4.5 V.
16 VCC power_in Positive power supply; operating range 2 V to 6 V; ICC max 80 µA at VCC = 6 V, 25°C; decouple with 0.1 µF capacitor placed as close to pin as possible.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74HC165APWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc165apwr-etched.step / sn74hc165apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc165apwr.step / sn74hc165apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 047f2f8fa6295020, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF