SN74HC165

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74hc165",
  "title": "SN74HC165",
  "brief": "TI 8-bit parallel-in serial-out shift register, SOIC-16. Complementary serial outputs, cascadable, 2-6 V. Datasheet-verified.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "shift-register",
    "piso",
    "74hc",
    "soic-16",
    "texas-instruments"
  ],
  "component": {
    "mpn": "SN74HC165",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic IC",
    "subcategory": "8-bit PISO shift register",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc165.pdf",
    "parts": {
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      "footprint": "sn74hc165.kicad_mod",
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      "lbr": "sn74hc165.lbr",
      "model_3d_step": "sn74hc165-etched.step",
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    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "SH/LD",
        "type": "input",
        "description": "Shift or Load input (active-low load). When high, data is shifted on the rising edge of CLK. When low, data is asynchronously loaded from the parallel inputs A-H, independent of CLK/CLK INH/SER levels."
      },
      {
        "number": "2",
        "name": "CLK",
        "type": "input",
        "description": "Clock input. On a low-to-high transition (with SH/LD high and CLK INH low) data is shifted one bit toward the QH serial output."
      },
      {
        "number": "3",
        "name": "E",
        "type": "input",
        "description": "Parallel data input E. Loaded into stage E of the register while SH/LD is low."
      },
      {
        "number": "4",
        "name": "F",
        "type": "input",
        "description": "Parallel data input F. Loaded into stage F of the register while SH/LD is low."
      },
      {
        "number": "5",
        "name": "G",
        "type": "input",
        "description": "Parallel data input G. Loaded into stage G of the register while SH/LD is low."
      },
      {
        "number": "6",
        "name": "H",
        "type": "input",
        "description": "Parallel data input H (the last stage before the QH serial output). Loaded into stage H of the register while SH/LD is low."
      },
      {
        "number": "7",
        "name": "/QH",
        "type": "output",
        "description": "Complementary serial output - the logical inverse of the last-stage (H) flip-flop. Drives ±4 mA at VCC = 5 V; up to 10 LSTTL loads."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V) for the device."
      },
      {
        "number": "9",
        "name": "QH",
        "type": "output",
        "description": "Serial output - the state of the last-stage (H) flip-flop. Data shifted through the register appears here bit-by-bit on each CLK rising edge. Drives ±4 mA at VCC = 5 V; up to 10 LSTTL loads."
      },
      {
        "number": "10",
        "name": "SER",
        "type": "input",
        "description": "Serial data input. Feeds the first stage (A) of the register when SH/LD is high; sampled on the rising edge of CLK."
      },
      {
        "number": "11",
        "name": "A",
        "type": "input",
        "description": "Parallel data input A (the first stage, adjacent to SER). Loaded into stage A of the register while SH/LD is low."
      },
      {
        "number": "12",
        "name": "B",
        "type": "input",
        "description": "Parallel data input B. Loaded into stage B of the register while SH/LD is low."
      },
      {
        "number": "13",
        "name": "C",
        "type": "input",
        "description": "Parallel data input C. Loaded into stage C of the register while SH/LD is low."
      },
      {
        "number": "14",
        "name": "D",
        "type": "input",
        "description": "Parallel data input D. Loaded into stage D of the register while SH/LD is low."
      },
      {
        "number": "15",
        "name": "CLK INH",
        "type": "input",
        "description": "Clock inhibit. When high, no shifting occurs; functionally interchangeable with CLK (either input can serve as clock while the other is held low). Must be transitioned high only while CLK is high to avoid a double-clock."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply, 2 V to 6 V (5 V nominal). Absolute maximum 7 V. Bypass with a local ceramic capacitor to GND."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74hc165.pdf",
        "pages": 37,
        "sha256": "517390062d4006fc",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74HC165",
      "logic_family": "74HC",
      "function_code": "165",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit PISO Shift Register",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
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        "checked": "2026-10-07",
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        "checked": "2026-10-07",
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    ]
  },
  "metadata": {
    "specs": {
      "Type": "8-bit PISO shift register",
      "Load": "parallel (SH/LD low latches A-H)",
      "Serial out": "QH + complementary /QH",
      "Cascade": "SER input + CLK INH",
      "Shift direction": "MSB first",
      "Logic family": "HC (high-speed CMOS)",
      "Supply voltage": "2-6 V",
      "Package": "SOIC-16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74hc165",
    "74hc165",
    "parallel to serial",
    "piso shift register",
    "read many inputs"
  ],
  "discovery_pitch": "SN74HC165 8-bit parallel-in serial-out shift register (SOIC-16) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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  "variants": [
    {
      "mpn": "SN74HC165D (SOIC-16, tube)",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC165DR (SOIC-16, tape & reel)",
      "kind": "packaging"
    }
  ]
}