component
SN74HC164DR
Public Made by Adomby adom
Texas Instruments Shifting Register, SOIC-14-150mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC164DR
Texas Instruments · Shifting Register · SOIC-14-150mil
SN74HC164DR from Texas Instruments, in a SOIC-14-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Gated Serial Input 1. AND-gated with input B to feed the first flip-flop; a low on either A or B inhibits new data entry and resets the first flip-flop low on the next CLK rising edge. |
| 2 | B | input | Gated Serial Input 2. AND-gated with input A to feed the first flip-flop; a low on either input inhibits new data entry. |
| 3 | QA | output | Parallel output, bit A (first stage of the 8-bit shift register). CMOS output rated for ±4 mA drive at 5 V. |
| 4 | QB | output | Parallel output, bit B (second stage of the shift register). CMOS output rated for ±4 mA drive at 5 V. |
| 5 | QC | output | Parallel output, bit C (third stage of the shift register). CMOS output rated for ±4 mA drive at 5 V. |
| 6 | QD | output | Parallel output, bit D (fourth stage of the shift register). CMOS output rated for ±4 mA drive at 5 V. |
| 7 | GND | power_in | Ground reference (0 V). Must be connected to the system ground. |
| 8 | CLK | input | Clock input. Data at the serial inputs is transferred into the shift register on the low-to-high transition of CLK. Max clock frequency 31 MHz at VCC=4.5 V. |
| 9 | CLR | input | Asynchronous clear, active-low. Driving CLR low forces all eight parallel outputs QA-QH low independent of the CLK and serial inputs. |
| 10 | QE | output | Parallel output, bit E (fifth stage of the shift register). CMOS output rated for ±4 mA drive at 5 V. |
| 11 | QF | output | Parallel output, bit F (sixth stage of the shift register). CMOS output rated for ±4 mA drive at 5 V. |
| 12 | QG | output | Parallel output, bit G (seventh stage of the shift register). CMOS output rated for ±4 mA drive at 5 V. |
| 13 | QH | output | Parallel output, bit H (eighth/last stage of the shift register). CMOS output rated for ±4 mA drive at 5 V; commonly used for daisy-chaining to the serial input of a downstream '164. |
| 14 | VCC | power_in | Positive supply, 2 V to 6 V (5 V nominal). Recommended 0.1 µF bypass capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14-150mil |
| Category | Logic |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
SN74HC164DRSN74HC164DRNSSN74HC164DRPWSN74HC164DRJSN74HC164DRWSN74HC164DRFK
CAD (KiCad official)
- Symbol:
SN74HC164DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14-150mil (KiCad packages3D, STEP)
- 3D model files:
sn74hc164dr-etched.step/sn74hc164dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc164dr.step/sn74hc164dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
51860c45fddf000a, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).