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SN74HC163IPWRG4Q1
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Texas Instruments Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# SN74HC163IPWRG4Q1++**Texas Instruments** · Counters, Dividers · TSSOP-16++SN74HC163IPWRG4Q1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLR | input | Synchronous clear input (active low); resets all flip-flop outputs low on next CLK rising edge, independent of enable inputs. |+| 2 | CLK | input | Clock input; triggers all four flip-flops on rising edge; maximum operating frequency 6-44 MHz depending on VCC and temperature. |+| 3 | A | input | Preset data input A; loaded into QA when LOAD is low after next CLK pulse; setup time 26-38 ns before CLK. |+| 4 | B | input | Preset data input B; loaded into QB when LOAD is low after next CLK pulse; setup time 26-38 ns before CLK. |+| 5 | C | input | Preset data input C; loaded into QC when LOAD is low after next CLK pulse; setup time 26-38 ns before CLK. |+| 6 | D | input | Preset data input D; loaded into QD when LOAD is low after next CLK pulse; setup time 26-38 ns before CLK. |+| 7 | ENP | input | Count enable input (active high); counting occurs only when both ENP and ENT are high; setup time 29-38 ns before CLK. |+| 8 | GND | power_in | Ground reference (0 V); maximum continuous current ±50 mA. |+| 9 | LOAD | input | Synchronous load input (active low); causes outputs to load preset data after next CLK pulse; setup time 23-29 ns before CLK. |+| 10 | ENT | input | Synchronous toggle/count enable input (active high); counting requires both ENT and ENP high; fed forward to enable RCO; setup time 29-43 ns before CLK. |+| 11 | QD | output | Output of D flip-flop (least significant bit); maximum output current ±25 mA continuous; propagation delay 21-51 ns from CLK rising edge. |+| 12 | QC | output | Output of C flip-flop; maximum output current ±25 mA continuous; propagation delay 21-51 ns from CLK rising edge. |+| 13 | QB | output | Output of B flip-flop; maximum output current ±25 mA continuous; propagation delay 21-51 ns from CLK rising edge. |+| 14 | QA | output | Output of A flip-flop (most significant bit); maximum output current ±25 mA continuous; propagation delay 21-51 ns from CLK rising edge. |+| 15 | RCO | output | Ripple carry output (active high); produces high-level pulse when counter reaches maximum count (9 or 15 with QA high); propagation delay 20-54 ns from CLK. |+| 16 | VCC | power_in | Supply voltage; recommended operating range 2 V to 6 V; maximum continuous current ±50 mA. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `SN74HC163IPWRG4Q1`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `sn74hc163ipwrg4q1-etched.step` / `sn74hc163ipwrg4q1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc163ipwrg4q1.step` / `sn74hc163ipwrg4q1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hc163-q1) (20 pp, sha256 `6675e23ba20c09b0`, retrieved 2026-10-03, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74hc163ipwrg4q1-datasheet.pdf)
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resets all flip-flop outputs low on next CLK rising edge, independent of enable inputs."+ },+ {+ "number": "2",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; triggers all four flip-flops on rising edge; maximum operating frequency 6-44 MHz depending on VCC and temperature."+ },+ {+ "number": "3",+ "name": "A",+ "type": "input",+ "description": "Preset data input A; loaded into QA when LOAD is low after next CLK pulse; setup time 26-38 ns before CLK."+ },+ {+ "number": "4",+ "name": "B",+ "type": "input",+ "description": "Preset data input B; loaded into QB when LOAD is low after next CLK pulse; setup time 26-38 ns before CLK."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Preset data input C; loaded into QC when LOAD is low after next CLK pulse; setup time 26-38 ns before CLK."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Preset data input D; loaded into QD when LOAD is low after next CLK pulse; setup time 26-38 ns before CLK."+ },+ {+ "number": "7",+ "name": "ENP",+ "type": "input",+ "description": "Count enable input (active high); counting occurs only when both ENP and ENT are high; setup time 29-38 ns before CLK."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V); maximum continuous current ±50 mA."+ },+ {+ "number": "9",+ "name": "LOAD",+ "type": "input",+ "description": "Synchronous load input (active low); causes outputs to load preset data after next CLK pulse; setup time 23-29 ns before CLK."+ },+ {+ "number": "10",+ "name": "ENT",+ "type": "input",+ "description": "Synchronous toggle/count enable input (active high); counting requires both ENT and ENP high; fed forward to enable RCO; setup time 29-43 ns before CLK."+ },+ {+ "number": "11",+ "name": "QD",+ "type": "output",+ "description": "Output of D flip-flop (least significant bit); maximum output current ±25 mA continuous; propagation delay 21-51 ns from CLK rising edge."+ },+ {+ "number": "12",+ "name": "QC",+ "type": "output",+ "description": "Output of C flip-flop; maximum output current ±25 mA continuous; propagation delay 21-51 ns from CLK rising edge."+ },+ {+ "number": "13",+ "name": "QB",+ "type": "output",+ "description": "Output of B flip-flop; maximum output current ±25 mA continuous; propagation delay 21-51 ns from CLK rising edge."+ },+ {+ "number": "14",+ "name": "QA",+ "type": "output",+ "description": "Output of A flip-flop (most significant bit); maximum output current ±25 mA continuous; propagation delay 21-51 ns from CLK rising edge."+ },+ {+ "number": "15",+ "name": "RCO",+ "type": "output",+ "description": "Ripple carry output (active high); produces high-level pulse when counter reaches maximum count (9 or 15 with QA high); propagation delay 20-54 ns from CLK."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; recommended operating range 2 V to 6 V; maximum continuous current ±50 mA."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 20,+ "cost_usd": 0.1584,+ "at": "2026-10-03T05:28:00"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74hc163-q1",+ "pages": 20,+ "sha256": "6675e23ba20c09b0",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}