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SN74HC163DR

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Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74HC163DR

Texas Instruments · Counters, Dividers · SOIC-16

SN74HC163DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low synchronous clear: a low level sets all four flip-flop outputs low after the next low-to-high CLK transition, regardless of the enable inputs.
2 CLK input Buffered clock input; the four flip-flops trigger on the rising (positive-going) edge of CLK.
3 A input Parallel preset data input (bit A); when LOAD is low, the outputs take the preset data after the next clock pulse. Unused inputs must be held at VCC or GND.
4 B input Parallel preset data input (bit B); when LOAD is low, the outputs take the preset data after the next clock pulse. Unused inputs must be held at VCC or GND.
5 C input Parallel preset data input (bit C); when LOAD is low, the outputs take the preset data after the next clock pulse. Unused inputs must be held at VCC or GND.
6 D input Parallel preset data input (bit D); when LOAD is low, the outputs take the preset data after the next clock pulse. Unused inputs must be held at VCC or GND.
7 ENP input Count-enable input; both ENP and ENT must be high for the counter to count, and transitions at ENP are allowed regardless of the CLK level.
8 GND power_in Ground reference; the absolute maximum continuous current through VCC or GND is ±50 mA.
9 LOAD input Active-low synchronous preset input; a low level disables the counter and loads the A-D data on the next clock pulse regardless of the enable inputs.
10 ENT input Count-enable input that also feeds forward to enable RCO; both ENP and ENT must be high to count.
11 QD output Counter output bit D (most significant bit of the 4-bit binary count); outputs can drive up to 10 LSTTL loads.
12 QC output Counter output bit C; outputs can drive up to 10 LSTTL loads.
13 QB output Counter output bit B; outputs can drive up to 10 LSTTL loads.
14 QA output Counter output bit A (least significant bit); outputs can drive up to 10 LSTTL loads.
15 RCO output Ripple-carry output that produces a high-level pulse while the count is maximum (9 or 15 with QA high) when ENT is high, for cascading stages.
16 VCC power_in Supply voltage: recommended operating range 2 V to 6 V (5 V nominal), absolute maximum −0.5 V to 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 5 6 V 6
High-level input voltage VIH 1.5 V VCC = 2 V 6
High-level input voltage VIH 3.15 V VCC = 4.5 V 6
High-level input voltage VIH 4.2 V VCC = 6 V 6
Low-level input voltage VIL 0.5 V VCC = 2 V 6
Low-level input voltage VIL 1.35 V VCC = 4.5 V 6
Low-level input voltage VIL 1.8 V VCC = 6 V 6
Input transition rise/fall time Δt/Δv 1000 ns VCC = 2 V 6
Input transition rise/fall time Δt/Δv 500 ns VCC = 4.5 V 6
Input transition rise/fall time Δt/Δv 400 ns VCC = 6 V 6
Operating free-air temperature TA -40 85 °C SN74HC163 6
Supply voltage range VCC -0.5 7 V 6
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 6
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 6
Continuous output current IO -25 25 mA VO = 0 to VCC 6
Continuous current through VCC or GND -50 50 mA 6
Package thermal impedance, D package θJA 73 °C/W D package 6
Storage temperature range Tstg -65 150 °C 6
High-level output voltage VOH 1.9 V VI = VIH or VIL, IOH = −20 µA, VCC = 2 V 7
High-level output voltage VOH 4.4 V VI = VIH or VIL, IOH = −20 µA, VCC = 4.5 V 7
High-level output voltage VOH 5.9 V VI = VIH or VIL, IOH = −20 µA, VCC = 6 V 7
High-level output voltage VOH 3.84 V VI = VIH or VIL, IOH = −4 mA, VCC = 4.5 V 7
High-level output voltage VOH 5.34 V VI = VIH or VIL, IOH = −5.2 mA, VCC = 6 V 7
Low-level output voltage VOL 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC = 2 V 7
Low-level output voltage VOL 0.33 V VI = VIH or VIL, IOL = 4 mA, VCC = 4.5 V 7
Input current II -1000 1000 nA VI = VCC or 0, VCC = 6 V 7
Supply current ICC 80 µA VI = VCC or 0, IO = 0, VCC = 6 V 7
Input capacitance Ci 10 pF VCC = 2 V to 6 V 7
Clock frequency fclock 5 MHz VCC = 2 V 7
Clock frequency fclock 25 MHz VCC = 4.5 V 7
Clock frequency fclock 29 MHz VCC = 6 V 7
Pulse duration CLK high or low tw 100 ns VCC = 2 V 7
Pulse duration CLK high or low tw 20 ns VCC = 4.5 V 7
Pulse duration CLK high or low tw 17 ns VCC = 6 V 7
Setup time before CLK↑, A, B, C, or D tsu 190 ns VCC = 2 V 7
Setup time before CLK↑, A, B, C, or D tsu 38 ns VCC = 4.5 V 7
Setup time before CLK↑, A, B, C, or D tsu 32 ns VCC = 6 V 7
Setup time before CLK↑, ENP or ENT tsu 215 ns VCC = 2 V 7
Setup time before CLK↑, ENP or ENT tsu 43 ns VCC = 4.5 V 7
Setup time before CLK↑, ENP or ENT tsu 37 ns VCC = 6 V 7
Maximum clock frequency (fmax) fmax 5 MHz VCC = 2 V, CL = 50 pF 8
Maximum clock frequency (fmax) fmax 25 MHz VCC = 4.5 V, CL = 50 pF 8
Maximum clock frequency (fmax) fmax 29 MHz VCC = 6 V, CL = 50 pF 8
Propagation delay CLK to RCO tpd 270 ns CLK→RCO, VCC = 2 V, CL = 50 pF 8
Propagation delay CLK to RCO tpd 54 ns CLK→RCO, VCC = 4.5 V, CL = 50 pF 8
Propagation delay CLK to RCO tpd 46 ns CLK→RCO, VCC = 6 V, CL = 50 pF 8
Propagation delay CLK to any Q tpd 255 ns CLK→any Q, VCC = 2 V, CL = 50 pF 8
Propagation delay CLK to any Q tpd 51 ns CLK→any Q, VCC = 4.5 V, CL = 50 pF 8
Propagation delay CLK to any Q tpd 43 ns CLK→any Q, VCC = 6 V, CL = 50 pF 8
Propagation delay ENT to RCO tpd 245 ns ENT→RCO, VCC = 2 V, CL = 50 pF 8
Propagation delay ENT to RCO tpd 49 ns ENT→RCO, VCC = 4.5 V, CL = 50 pF 8
Propagation delay ENT to RCO tpd 42 ns ENT→RCO, VCC = 6 V, CL = 50 pF 8
Output transition time tt 95 ns VCC = 2 V, CL = 50 pF 8
Output transition time tt 19 ns VCC = 4.5 V, CL = 50 pF 8
Output transition time tt 16 ns VCC = 6 V, CL = 50 pF 8

CAD (KiCad official)

  • Symbol: SN74HC163DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc163dr-etched.step / sn74hc163dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc163dr.step / sn74hc163dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 7033099817317f28, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF