component
SN74HC160N
Public Made by Adomby adom
XBLW Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74HC160N
XBLW · Counters, Dividers · DIP-16
SN74HC160N from XBLW, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Asynchronous master reset, active LOW; a LOW sets Q0 to Q3 LOW regardless of CP, PE, CET and CEP. |
| 2 | CP | input | Clock input, LOW-to-HIGH edge triggered. |
| 3 | D0 | input | Data input, loaded into the counter on the positive-going clock edge when PE is LOW. |
| 4 | D1 | input | Data input, loaded into the counter on the positive-going clock edge when PE is LOW. |
| 5 | D2 | input | Data input, loaded into the counter on the positive-going clock edge when PE is LOW. |
| 6 | D3 | input | Data input, loaded into the counter on the positive-going clock edge when PE is LOW. |
| 7 | CEP | input | Count enable input; both CEP and CET must be HIGH to count. |
| 8 | GND | power_in | Ground (0 V). |
| 9 | PE | input | Parallel enable input, active LOW; disables counting and loads D0 to D3 on the positive-going clock edge. |
| 10 | CET | input | Count enable carry input; must be HIGH to count and enables the terminal count output TC. |
| 11 | Q3 | output | Flip-flop output. |
| 12 | Q2 | output | Flip-flop output. |
| 13 | Q1 | output | Flip-flop output. |
| 14 | Q0 | output | Flip-flop output. |
| 15 | TC | output | Terminal count output; produces a HIGH pulse approximately equal in duration to a HIGH output of Q0. |
| 16 | VCC | power_in | Supply voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XBLW |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74HC160N - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hc160n-etched.step/sn74hc160n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc160n.step/sn74hc160n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XBLW datasheet (23 pp, sha256
0cbff34f6893b3bb, retrieved 2026-10-13, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HC160N
**XBLW** · Counters, Dividers · DIP-16
SN74HC160N from XBLW, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Asynchronous master reset, active LOW; a LOW sets Q0 to Q3 LOW regardless of CP, PE, CET and CEP. |
| 2 | CP | input | Clock input, LOW-to-HIGH edge triggered. |
| 3 | D0 | input | Data input, loaded into the counter on the positive-going clock edge when PE is LOW. |
| 4 | D1 | input | Data input, loaded into the counter on the positive-going clock edge when PE is LOW. |
| 5 | D2 | input | Data input, loaded into the counter on the positive-going clock edge when PE is LOW. |
| 6 | D3 | input | Data input, loaded into the counter on the positive-going clock edge when PE is LOW. |
| 7 | CEP | input | Count enable input; both CEP and CET must be HIGH to count. |
| 8 | GND | power_in | Ground (0 V). |
| 9 | PE | input | Parallel enable input, active LOW; disables counting and loads D0 to D3 on the positive-going clock edge. |
| 10 | CET | input | Count enable carry input; must be HIGH to count and enables the terminal count output TC. |
| 11 | Q3 | output | Flip-flop output. |
| 12 | Q2 | output | Flip-flop output. |
| 13 | Q1 | output | Flip-flop output. |
| 14 | Q0 | output | Flip-flop output. |
| 15 | TC | output | Terminal count output; produces a HIGH pulse approximately equal in duration to a HIGH output of Q0. |
| 16 | VCC | power_in | Supply voltage. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XBLW |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `SN74HC160N`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hc160n-etched.step` / `sn74hc160n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc160n.step` / `sn74hc160n.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XBLW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590907584537190400) (23 pp, sha256 `0cbff34f6893b3bb`, retrieved 2026-10-13, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hc160n-datasheet.pdf)