# SN74HC160DR

**lingxingic** · Counters, Dividers · SOP-16

SN74HC160DR from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Asynchronous master reset, active LOW: a LOW sets Q0 to Q3 LOW regardless of the levels on CP, PE, CET and CEP. |
| 2 | CP | input | Clock input, positive (LOW-to-HIGH) edge triggered; all flip-flops are clocked simultaneously on this edge. |
| 3 | D0 | input | Parallel data input D0, loaded into the counter on the positive clock edge when PE is LOW. |
| 4 | D1 | input | Parallel data input D1, loaded into the counter on the positive clock edge when PE is LOW. |
| 5 | D2 | input | Parallel data input D2, loaded into the counter on the positive clock edge when PE is LOW. |
| 6 | D3 | input | Parallel data input D3, loaded into the counter on the positive clock edge when PE is LOW. |
| 7 | CEP | input | Count enable input; CEP and CET must both be HIGH (set up before the clock edge) for the counter to count. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages. |
| 9 | PE | input | Parallel enable input, active LOW: a LOW disables counting and loads D0 to D3 into the counter on the positive clock edge. |
| 10 | CET | input | Count enable carry input; must be HIGH to count and is fed forward to enable the TC output. |
| 11 | Q3 | output | Flip-flop output Q3 of the 4-bit BCD counter. |
| 12 | Q2 | output | Flip-flop output Q2 of the 4-bit BCD counter. |
| 13 | Q1 | output | Flip-flop output Q1 of the 4-bit BCD counter. |
| 14 | Q0 | output | Flip-flop output Q0 of the 4-bit BCD counter. |
| 15 | TC | output | Terminal count output; goes HIGH when CET is HIGH and the counter is at terminal count (HLLH), giving a pulse used to enable the next cascaded stage. |
| 16 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 6.0 V for SN74HC160 (4.5 V to 5.5 V for SN74HCT160). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 |  | 7 | V |  | 7 |
| input clamping current | IIK | -20 |  | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 7 |
| output clamping current | IOK | -20 |  | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 7 |
| output current | IO | -25 |  | 25 | mA | -0.5V < VO < VCC+0.5V | 7 |
| supply current | ICC |  |  | 50 | mA |  | 7 |
| ground current | IGND | -50 |  |  | mA |  | 7 |
| storage temperature | Tstg | -65 |  | 150 | ℃ |  | 7 |
| total power dissipation | Ptot |  |  | 500 | mW | SOP16: above 70℃ derates 8mW/K | 7 |
| soldering temperature | TL |  |  | 250 | ℃ | 10s; SOP package | 7 |
| supply voltage | VCC | 2 | 5 | 6 | V | SN74HC160 | 8 |
| input voltage | VI | 0 |  |  | V | SN74HC160 | 8 |
| output voltage | VO | 0 |  |  | V | SN74HC160 | 8 |
| input transition rise and fall rate | Δt/ΔV |  |  | 625 | ns/V | VCC=2.0V | 8 |
| input transition rise and fall rate | Δt/ΔV |  | 1.67 | 139 | ns/V | VCC=4.5V | 8 |
| input transition rise and fall rate | Δt/ΔV |  |  | 83 | ns/V | VCC=6.0V | 8 |
| ambient temperature | Tamb | -40 |  | 105 | ℃ | SN74HC160 | 8 |
| HIGH-level input voltage | VIH | 1.5 | 1.2 |  | V | Tamb=25℃; VCC=2.0V | 8 |
| HIGH-level input voltage | VIH | 3.15 | 2.4 |  | V | Tamb=25℃; VCC=4.5V | 8 |
| HIGH-level input voltage | VIH | 4.2 | 3.2 |  | V | Tamb=25℃; VCC=6.0V | 8 |
| LOW-level input voltage | VIL |  | 0.8 | 0.5 | V | Tamb=25℃; VCC=2.0V | 8 |
| LOW-level input voltage | VIL |  | 2.1 | 1.35 | V | Tamb=25℃; VCC=4.5V | 8 |
| LOW-level input voltage | VIL |  | 2.8 | 1.8 | V | Tamb=25℃; VCC=6.0V | 8 |
| HIGH-level output voltage | VOH | 1.9 | 2 |  | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 8 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 |  | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 8 |
| HIGH-level output voltage | VOH | 5.9 | 6 |  | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 8 |
| HIGH-level output voltage | VOH | 3.98 | 4.32 |  | V | Tamb=25℃; VI=VIH or VIL; IO=-4.0mA; VCC=4.5V | 8 |
| HIGH-level output voltage | VOH | 5.48 | 5.81 |  | V | Tamb=25℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 8 |
| LOW-level output voltage | VOL |  | 0 | 0.1 | V | Tamb=25℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 8 |
| LOW-level output voltage | VOL |  | 0.15 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=4.0mA; VCC=4.5V | 8 |
| LOW-level output voltage | VOL |  | 0.16 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=5.2mA; VCC=6.0V | 8 |
| input leakage current | II | -0.1 |  | 0.1 | uA | Tamb=25℃; VI=VCC or GND; VCC=6.0V | 8 |
| supply current | ICC |  |  | 8 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 8 |
| HIGH-level input voltage | VIH | 1.5 |  |  | V | Tamb=-40℃ to +105℃; VCC=2.0V | 10 |
| HIGH-level input voltage | VIH | 3.15 |  |  | V | Tamb=-40℃ to +105℃; VCC=4.5V | 10 |
| HIGH-level input voltage | VIH | 4.2 |  |  | V | Tamb=-40℃ to +105℃; VCC=6.0V | 10 |
| LOW-level input voltage | VIL |  |  | 0.5 | V | Tamb=-40℃ to +105℃; VCC=2.0V | 10 |
| LOW-level input voltage | VIL |  |  | 1.35 | V | Tamb=-40℃ to +105℃; VCC=4.5V | 10 |
| LOW-level input voltage | VIL |  |  | 1.8 | V | Tamb=-40℃ to +105℃; VCC=6.0V | 10 |
| HIGH-level output voltage | VOH | 1.9 |  |  | V | Tamb=-40℃ to +105℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 10 |
| HIGH-level output voltage | VOH | 4.4 |  |  | V | Tamb=-40℃ to +105℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 10 |
| HIGH-level output voltage | VOH | 5.9 |  |  | V | Tamb=-40℃ to +105℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 10 |
| HIGH-level output voltage | VOH | 3.7 |  |  | V | Tamb=-40℃ to +105℃; VI=VIH or VIL; IO=-4.0mA; VCC=4.5V | 10 |
| HIGH-level output voltage | VOH | 5.2 |  |  | V | Tamb=-40℃ to +105℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 10 |
| LOW-level output voltage | VOL |  |  | 0.1 | V | Tamb=-40℃ to +105℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 10 |
| LOW-level output voltage | VOL |  |  | 0.4 | V | Tamb=-40℃ to +105℃; VI=VIH or VIL; IO=4.0mA; VCC=4.5V | 10 |
| input leakage current | II | -1 |  | 1 | uA | Tamb=-40℃ to +105℃; VI=VCC or GND; VCC=6.0V | 10 |
| supply current | ICC |  |  | 160 | uA | Tamb=-40℃ to +105℃; VI=VCC or GND; IO=0A; VCC=6.0V | 11 |
| propagation delay CP to Qn | tpd |  |  | 56 | ns | Tamb=-40℃ to +105℃; VCC=4.5V; see Figure 8 | 15 |
| propagation delay CP to TC | tpd |  |  | 65 | ns | Tamb=-40℃ to +105℃; VCC=4.5V; see Figure 8 | 15 |
| maximum frequency CP | fmax | 20 |  |  | MHz | Tamb=-40℃ to +105℃; VCC=4.5V; see Figure 8 | 16 |
| pulse width CP HIGH or LOW | tW | 24 |  |  | ns | Tamb=-40℃ to +105℃; VCC=4.5V; see Figure 8 | 16 |
| set-up time Dn to CP | tsu | 24 |  |  | ns | Tamb=-40℃ to +105℃; VCC=4.5V; see Figure 11 | 16 |

## CAD (KiCad official)

- Symbol: `SN74HC160DR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hc160dr-etched.step` / `sn74hc160dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc160dr.step` / `sn74hc160dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603392385250979840) (23 pp, sha256 `776f0a46e2c586f2`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74hc160dr-datasheet.pdf)