component
SN74HC13DR
Public Made by Adomby adom
lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 8d ago |
| viewers | 8d ago |
| package.json | 8d ago |
| page.json | 8d ago |
| README.md | 8d ago |
| sn74hc13dr-etched.glb | 8d ago |
| sn74hc13dr-etched.step | 8d ago |
| sn74hc13dr-hero.glb | 8d ago |
| sn74hc13dr-hero.overlay.json | 8d ago |
| sn74hc13dr.glb | 8d ago |
| sn74hc13dr.kicad_mod | 8d ago |
| sn74hc13dr.kicad_sym | 8d ago |
| sn74hc13dr.lbr | 8d ago |
| sn74hc13dr.step | 8d ago |
SN74HC13DR
lingxingic · Logic Gates · SOP-14
SN74HC13DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of NAND gate 1, a Schmitt-trigger input; per the function table, a LOW on any input forces 1Y HIGH. |
| 2 | 1B | input | Data input 1B of NAND gate 1, a Schmitt-trigger input; per the function table, a LOW on any input forces 1Y HIGH. |
| 3 | n.c. | unconnected | Not connected; the datasheet gives no internal connection for this pin. |
| 4 | 1C | input | Data input 1C of NAND gate 1, a Schmitt-trigger input; per the function table, a LOW on any input forces 1Y HIGH. |
| 5 | 1D | input | Data input 1D of NAND gate 1, a Schmitt-trigger input; per the function table, a LOW on any input forces 1Y HIGH. |
| 6 | 1Y | output | Data output 1Y of NAND gate 1; it goes LOW only when all four inputs 1A to 1D are HIGH. |
| 7 | GND | power_in | Ground reference (0 V) for the device. |
| 8 | 2Y | output | Data output 2Y of NAND gate 2; it goes LOW only when all four inputs 2A to 2D are HIGH. |
| 9 | 2A | input | Data input 2A of NAND gate 2, a Schmitt-trigger input; per the function table, a LOW on any input forces 2Y HIGH. |
| 10 | 2B | input | Data input 2B of NAND gate 2, a Schmitt-trigger input; per the function table, a LOW on any input forces 2Y HIGH. |
| 11 | n.c. | unconnected | Not connected; the datasheet gives no internal connection for this pin. |
| 12 | 2C | input | Data input 2C of NAND gate 2, a Schmitt-trigger input; per the function table, a LOW on any input forces 2Y HIGH. |
| 13 | 2D | input | Data input 2D of NAND gate 2, a Schmitt-trigger input; per the function table, a LOW on any input forces 2Y HIGH. |
| 14 | VCC | power_in | Supply voltage; for the SN74HC13 the recommended range is 2.0 V to 6.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| supply current | ICC | 50 | mA | 5 | |||
| ground current | IGND | -50 | mA | 5 | |||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 5 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 5 | |
| output current | IO | -25 | 25 | mA | -0.5V < VO < VCC+0.5V | 5 | |
| storage temperature | Tstg | -65 | 150 | ℃ | 5 | ||
| soldering temperature | TL | 260 | ℃ | 10s; SOP/TSSOP | 5 | ||
| supply voltage | VCC | 2 | 5 | 6 | V | SN74HC13 | 5 |
| input voltage | VI | 0 | V | SN74HC13; max = VCC (not numeric) | 5 | ||
| output voltage | VO | 0 | V | SN74HC13; max = VCC (not numeric) | 5 | ||
| ambient temperature | Tamb | -40 | 125 | ℃ | SN74HC13 | 5 | |
| positive-going threshold voltage | VT+ | 0.7 | 1.18 | 1.5 | V | Tamb -40 to +85℃; VCC 2.0V | 6 |
| positive-going threshold voltage | VT+ | 1.7 | 2.38 | 3.15 | V | Tamb -40 to +85℃; VCC 4.5V | 6 |
| positive-going threshold voltage | VT+ | 2.1 | 3.14 | 4.2 | V | Tamb -40 to +85℃; VCC 6.0V | 6 |
| negative-going threshold voltage | VT- | 0.3 | 0.52 | 0.9 | V | Tamb -40 to +85℃; VCC 2.0V | 6 |
| negative-going threshold voltage | VT- | 0.9 | 1.4 | 2 | V | Tamb -40 to +85℃; VCC 4.5V | 6 |
| negative-going threshold voltage | VT- | 1.2 | 1.89 | 2.6 | V | Tamb -40 to +85℃; VCC 6.0V | 6 |
| hysteresis voltage | VH | 0.2 | 0.66 | 1 | V | Tamb -40 to +85℃; VCC 2.0V | 6 |
| hysteresis voltage | VH | 0.4 | 0.98 | 1.4 | V | Tamb -40 to +85℃; VCC 4.5V | 6 |
| hysteresis voltage | VH | 0.6 | 1.25 | 1.6 | V | Tamb -40 to +85℃; VCC 6.0V | 6 |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | Tamb -40 to +85℃; VCC 2.0V; IO=-20uA | 6 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | Tamb -40 to +85℃; VCC 4.5V; IO=-20uA | 6 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | Tamb -40 to +85℃; VCC 6.0V; IO=-20uA | 6 | |
| HIGH-level output voltage | VOH | 3.84 | 4.32 | V | Tamb -40 to +85℃; VCC 4.5V; IO=-4.0mA | 6 | |
| HIGH-level output voltage | VOH | 5.34 | 5.81 | V | Tamb -40 to +85℃; VCC 6.0V; IO=-5.2mA | 6 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | Tamb -40 to +85℃; VCC 2.0V; IO=20uA | 6 | |
| LOW-level output voltage | VOL | 0.15 | 0.33 | V | Tamb -40 to +85℃; VCC 4.5V; IO=4.0mA | 6 | |
| LOW-level output voltage | VOL | 0.16 | 0.33 | V | Tamb -40 to +85℃; VCC 6.0V; IO=5.2mA | 6 | |
| input leakage current | II | -1 | 1 | uA | Tamb -40 to +85℃; VCC 6.0V; VI=VCC or GND | 6 | |
| supply current | ICC | 20 | uA | Tamb -40 to +85℃; VCC 6.0V; VI=VCC or GND; IO=0A | 6 | ||
| negative-going threshold voltage | VT- | 0.9 | 1.4 | 2 | V | Tamb -40 to +125℃; VCC 4.5V | 7 |
| HIGH-level output voltage | VOH | 1.9 | V | Tamb -40 to +125℃; VCC 2.0V; IO=-20uA | 7 | ||
| HIGH-level output voltage | VOH | 4.4 | V | Tamb -40 to +125℃; VCC 4.5V; IO=-20uA | 7 | ||
| HIGH-level output voltage | VOH | 5.9 | V | Tamb -40 to +125℃; VCC 6.0V; IO=-20uA | 7 | ||
| HIGH-level output voltage | VOH | 3.7 | V | Tamb -40 to +125℃; VCC 4.5V; IO=-4.0mA | 7 | ||
| HIGH-level output voltage | VOH | 5.2 | V | Tamb -40 to +125℃; VCC 6.0V; IO=-5.2mA | 7 | ||
| LOW-level output voltage | VOL | 0.1 | V | Tamb -40 to +125℃; VCC 2.0V; IO=20uA | 7 | ||
| LOW-level output voltage | VOL | 0.4 | V | Tamb -40 to +125℃; VCC 4.5V; IO=4.0mA | 7 | ||
| input leakage current | II | -1 | 1 | uA | Tamb -40 to +125℃; VCC 6.0V; VI=VCC or GND | 7 | |
| supply current | ICC | 40 | uA | Tamb -40 to +125℃; VCC 6.0V; VI=VCC or GND; IO=0A | 7 | ||
| propagation delay tPLH, tPHL | tPLH, tPHL | 190 | ns | Tamb -40 to +125℃; VCC 2.0V; CL=50pF; see Figure 4 | 8 | ||
| propagation delay tPLH, tPHL | tPLH, tPHL | 38 | ns | Tamb -40 to +125℃; VCC 4.5V; CL=50pF; see Figure 4 | 8 | ||
| propagation delay tPLH, tPHL | tPLH, tPHL | 32 | ns | Tamb -40 to +125℃; VCC 6.0V; CL=50pF; see Figure 4 | 8 | ||
| transition time tTHL, tTLH | tTHL, tTLH | 110 | ns | Tamb -40 to +125℃; VCC 2.0V; CL=50pF; see Figure 4 | 8 | ||
| transition time tTHL, tTLH | tTHL, tTLH | 22 | ns | Tamb -40 to +125℃; VCC 4.5V; CL=50pF; see Figure 4 | 8 | ||
| transition time tTHL, tTLH | tTHL, tTLH | 19 | ns | Tamb -40 to +125℃; VCC 6.0V; CL=50pF; see Figure 4 | 8 |
CAD (KiCad official)
- Symbol:
SN74HC13DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hc13dr-etched.step/sn74hc13dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc13dr.step/sn74hc13dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (14 pp, sha256
1d587d244e73988e, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).