SN74HC139 Dual 2-to-4 Decoder

@@ -1,8 +1,11 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "sn74hc139",+  "title": "SN74HC139 Dual 2-to-4 Decoder",+  "brief": "Dual 2-to-4 line decoder/demultiplexer with active-low outputs.",   "version": "0.1.0",-  "type": "component",-  "description": "Dual 2-to-4 line decoder/demultiplexer with active-low outputs.",+  "license": "CC-BY-SA-4.0",   "tags": [     "logic",     "decoder",@@ -11,6 +14,167 @@     "ti",     "soic-16"   ],+  "component": {+    "mpn": "SN74HC139",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-16",+    "pin_count": 16,+    "category": "Logic",+    "subcategory": "Decoder / Demultiplexer",+    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc139.pdf",+    "parts": {+      "symbol": "sn74hc139.kicad_sym",+      "footprint": "sn74hc139.kicad_mod",+      "model_3d": "sn74hc139.glb"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "1G",+        "type": "input",+        "description": "Decoder 1 active-low enable (strobe). When high, all 1Y0-1Y3 outputs are forced high; when low, the selected output is driven low. Can be used as a data input in demultiplexing applications."+      },+      {+        "number": "2",+        "name": "1A",+        "type": "input",+        "description": "Decoder 1 select input A (LSB of the 2-bit address for decoder 1)."+      },+      {+        "number": "3",+        "name": "1B",+        "type": "input",+        "description": "Decoder 1 select input B (MSB of the 2-bit address for decoder 1)."+      },+      {+        "number": "4",+        "name": "1Y0",+        "type": "output",+        "description": "Decoder 1 active-low output 0. Driven low when 1G=L and (1B,1A)=(0,0); otherwise high. IOH = -4 mA / IOL = 4 mA at VCC = 4.5 V."+      },+      {+        "number": "5",+        "name": "1Y1",+        "type": "output",+        "description": "Decoder 1 active-low output 1. Driven low when 1G=L and (1B,1A)=(0,1); otherwise high."+      },+      {+        "number": "6",+        "name": "1Y2",+        "type": "output",+        "description": "Decoder 1 active-low output 2. Driven low when 1G=L and (1B,1A)=(1,0); otherwise high."+      },+      {+        "number": "7",+        "name": "1Y3",+        "type": "output",+        "description": "Decoder 1 active-low output 3. Driven low when 1G=L and (1B,1A)=(1,1); otherwise high."+      },+      {+        "number": "8",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0 V) for both decoders."+      },+      {+        "number": "9",+        "name": "2Y3",+        "type": "output",+        "description": "Decoder 2 active-low output 3. Driven low when 2G=L and (2B,2A)=(1,1); otherwise high."+      },+      {+        "number": "10",+        "name": "2Y2",+        "type": "output",+        "description": "Decoder 2 active-low output 2. Driven low when 2G=L and (2B,2A)=(1,0); otherwise high."+      },+      {+        "number": "11",+        "name": "2Y1",+        "type": "output",+        "description": "Decoder 2 active-low output 1. Driven low when 2G=L and (2B,2A)=(0,1); otherwise high."+      },+      {+        "number": "12",+        "name": "2Y0",+        "type": "output",+        "description": "Decoder 2 active-low output 0. Driven low when 2G=L and (2B,2A)=(0,0); otherwise high."+      },+      {+        "number": "13",+        "name": "2B",+        "type": "input",+        "description": "Decoder 2 select input B (MSB of the 2-bit address for decoder 2)."+      },+      {+        "number": "14",+        "name": "2A",+        "type": "input",+        "description": "Decoder 2 select input A (LSB of the 2-bit address for decoder 2)."+      },+      {+        "number": "15",+        "name": "2G",+        "type": "input",+        "description": "Decoder 2 active-low enable (strobe). When high, all 2Y0-2Y3 outputs are forced high; when low, the selected output is driven low. Can be used as a data input in demultiplexing applications."+      },+      {+        "number": "16",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply, 2 V to 6 V (5 V nominal). Bypass with a 0.1 uF capacitor close to the pin (0.1 uF and 1 uF in parallel is common)."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/sn74hc139.pdf",+        "pages": 30,+        "sha256": "7bed90a2f9c2fe80",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Type": "Dual 2-to-4 decoder / demultiplexer",+      "Logic family": "74HC (CMOS)",+      "Outputs": "Active-low, one-of-four per decoder",+      "Supply voltage": "2 V to 6 V",+      "Propagation delay": "16 ns typ at 5 V",+      "Operating temperature": "-40 C to 85 C"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "2-to-4 decoder",+    "demultiplexer",+    "address decode",+    "chip select generation"+  ],+  "discovery_pitch": "Two independent 2-to-4 decoders for address decoding and generating chip selects.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -26,10 +190,5 @@     "docs/sn74hc139-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file