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SN74HC126N

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74hc126nfactory-2.0.0extractor-text

Verified SN74HC126N

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN74HC126N · DIP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 37-page datasheet
  • ✓distributor: lcsc C10422, digikey 2156-SN74HC126N-ND, mouser 595-SN74HC126N
  • ✓family: DIP-14_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-r3iar01m/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn74hc126n.kicad_sym✓ sn74hc126n.kicad_mod✓ sn74hc126n.step
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Contents

README

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SN74HC126N

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · DIP-14

SN74HC126N from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Input for channel 1 output enable.
2 1A input Input A for channel 1 buffer; each gate performs Y = A in positive logic.
3 1Y output Output Y of channel 1 buffer with 3-state output.
4 2OE input Input for channel 2 output enable.
5 2A input Input A for channel 2 buffer; each gate performs Y = A in positive logic.
6 2Y output Output Y of channel 2 buffer with 3-state output.
7 GND power_in Ground reference for the device.
8 3Y output Output Y of channel 3 buffer with 3-state output.
9 3A input Input A for channel 3 buffer; each gate performs Y = A in positive logic.
10 3OE input Input for channel 3 output enable.
11 4Y output Output Y of channel 4 buffer with 3-state output.
12 4A input Input A for channel 4 buffer; each gate performs Y = A in positive logic.
13 4OE input Input for channel 4 output enable.
14 VCC power_in Positive supply; recommended supply range is 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 2 5 6 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input voltage VI 0 V max VCC 4
Output voltage VO 0 V max VCC 4
Input transition time tt 1000 ns VCC = 2 V 4
Input transition time tt 500 ns VCC = 4.5 V 4
Input transition time tt 400 ns VCC = 6 V 4
Operating free-air temperature (SN74HC126) TA -40 85 °C SN74HC126 4
Junction-to-ambient thermal resistance (N PDIP) RθJA 62.5 °C/W N (PDIP) 14 pins 4
Junction-to-case (top) thermal resistance (N PDIP) RθJC(top) 50.2 °C/W N (PDIP) 14 pins 4
Junction-to-board thermal resistance (N PDIP) RθJB 42.2 °C/W N (PDIP) 14 pins 4
Junction-to-top characterization parameter (N PDIP) ΨJT 29.8 °C/W N (PDIP) 14 pins 4
Junction-to-board characterization parameter (N PDIP) ΨJB 42 °C/W N (PDIP) 14 pins 5
High-level output voltage VOH 1.9 1.998 V VI = VIH or VIL, IOH = -20 µA, VCC = 2 V; min -40°C to 85°C, typ 25°C 5
High-level output voltage VOH 4.4 4.499 V VI = VIH or VIL, IOH = -20 µA, VCC = 4.5 V; min -40°C to 85°C, typ 25°C 5
High-level output voltage VOH 5.9 5.999 V VI = VIH or VIL, IOH = -20 µA, VCC = 6 V; min -40°C to 85°C, typ 25°C 5
High-level output voltage VOH 3.84 4.3 V VI = VIH or VIL, IOH = -6 mA, VCC = 4.5 V; min -40°C to 85°C, typ 25°C 5
High-level output voltage VOH 5.34 5.8 V VI = VIH or VIL, IOH = -7.8 mA, VCC = 6 V; min -40°C to 85°C, typ 25°C 5
Low-level output voltage VOL 0.002 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC = 2 V; max -40°C to 85°C, typ 25°C 6
Low-level output voltage VOL 0.001 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC = 4.5 V; max -40°C to 85°C, typ 25°C 6
Low-level output voltage VOL 0.17 0.33 V VI = VIH or VIL, IOL = 6 mA, VCC = 4.5 V; max -40°C to 85°C, typ 25°C 6
Low-level output voltage VOL 0.15 0.33 V VI = VIH or VIL, IOL = 7.8 mA, VCC = 6 V; max -40°C to 85°C, typ 25°C 6
Input leakage current II -1 0.1 1 µA VI = VCC or 0, VCC = 6 V; max -40°C to 85°C, typ 25°C 5
Three-state leakage current IOZ -5 0.01 5 µA VO = VCC or 0, VCC = 6 V; max -40°C to 85°C, typ 25°C 5
Supply current ICC 8 80 µA VI = VCC or 0, IO = 0, VCC = 6 V; max -40°C to 85°C, typ 25°C 5
Input capacitance Ci 3 10 pF VCC = 2 V to 6 V; max -40°C to 85°C, typ 25°C 5
Propagation delay A to Y tpd 47 180 ns CL = 50 pF, VCC = 2 V; max -40°C to 85°C, typ 25°C 6
Propagation delay A to Y tpd 14 36 ns CL = 50 pF, VCC = 4.5 V; max -40°C to 85°C, typ 25°C 6
Propagation delay A to Y tpd 11 31 ns CL = 50 pF, VCC = 6 V; max -40°C to 85°C, typ 25°C 6
Propagation delay A to Y tpd 67 225 ns CL = 150 pF, VCC = 2 V; max -40°C to 85°C, typ 25°C 6
Propagation delay A to Y tpd 19 45 ns CL = 150 pF, VCC = 4.5 V; max -40°C to 85°C, typ 25°C 6
Propagation delay A to Y tpd 15 39 ns CL = 150 pF, VCC = 6 V; max -40°C to 85°C, typ 25°C 6
Enable delay OE to Y ten 57 180 ns CL = 50 pF, VCC = 2 V; max -40°C to 85°C, typ 25°C 6
Enable delay OE to Y ten 16 36 ns CL = 50 pF, VCC = 4.5 V; max -40°C to 85°C, typ 25°C 6
Enable delay OE to Y ten 12 31 ns CL = 50 pF, VCC = 6 V; max -40°C to 85°C, typ 25°C 6
Disable delay OE to Y tdis 35 180 ns CL = 50 pF, VCC = 2 V; max -40°C to 85°C, typ 25°C 6
Disable delay OE to Y tdis 17 36 ns CL = 50 pF, VCC = 4.5 V; max -40°C to 85°C, typ 25°C 6
Disable delay OE to Y tdis 15 31 ns CL = 50 pF, VCC = 6 V; max -40°C to 85°C, typ 25°C 6
Transition time Y tt 28 90 ns CL = 50 pF, VCC = 2 V; max -40°C to 85°C, typ 25°C 6
Transition time Y tt 8 18 ns CL = 50 pF, VCC = 4.5 V; max -40°C to 85°C, typ 25°C 6
Transition time Y tt 6 15 ns CL = 50 pF, VCC = 6 V; max -40°C to 85°C, typ 25°C 6
Transition time Y tt 45 315 ns CL = 150 pF, VCC = 2 V; max -40°C to 85°C, typ 25°C 6
Transition time Y tt 17 63 ns CL = 150 pF, VCC = 4.5 V; max -40°C to 85°C, typ 25°C 6
Transition time Y tt 13 53 ns CL = 150 pF, VCC = 6 V; max -40°C to 85°C, typ 25°C 6

CAD (KiCad official)

  • Symbol: SN74HC126N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74hc126n-etched.step / sn74hc126n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc126n.step / sn74hc126n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 8941286f02eac3b6, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF