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SN74HC112DR

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Texas Instruments Flip Flops, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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SN74HC112DR

Texas Instruments · Flip Flops · SOIC-16

SN74HC112DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLK input Flip-flop 1 clock input. Data at 1J/1K is transferred to 1Q on the negative (falling) edge of this clock.
2 1K input Flip-flop 1 K data input. Sampled on the falling edge of 1CLK per the J-K function table.
3 1J input Flip-flop 1 J data input. Sampled on the falling edge of 1CLK per the J-K function table.
4 1PRE input Flip-flop 1 asynchronous preset, active LOW. Driving low forces 1Q high regardless of clock, J, K.
5 1Q output Flip-flop 1 true (Q) output. Push-pull CMOS output capable of ±4 mA drive at VCC = 5 V.
6 1Q_N output Flip-flop 1 complementary (Q-bar) output. Push-pull CMOS output, complement of 1Q under normal operation.
7 2Q_N output Flip-flop 2 complementary (Q-bar) output. Push-pull CMOS output, complement of 2Q under normal operation.
8 GND power_in Ground reference (0 V) for the device.
9 2Q output Flip-flop 2 true (Q) output. Push-pull CMOS output capable of ±4 mA drive at VCC = 5 V.
10 2PRE input Flip-flop 2 asynchronous preset, active LOW. Driving low forces 2Q high regardless of clock, J, K.
11 2J input Flip-flop 2 J data input. Sampled on the falling edge of 2CLK per the J-K function table.
12 2K input Flip-flop 2 K data input. Sampled on the falling edge of 2CLK per the J-K function table.
13 2CLK input Flip-flop 2 clock input. Data at 2J/2K is transferred to 2Q on the negative (falling) edge of this clock.
14 2CLR input Flip-flop 2 asynchronous clear, active LOW. Driving low forces 2Q low regardless of clock, J, K.
15 1CLR input Flip-flop 1 asynchronous clear, active LOW. Driving low forces 1Q low regardless of clock, J, K.
16 VCC power_in Positive supply voltage, 2 V to 6 V recommended (7 V absolute maximum). Bypass with 0.1 uF close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • SN74HC112DRD
  • SN74HC112DR
  • SN74HC112DRG4
  • SN74HC112DRN
  • SN74HC112DRJ
  • SN74HC112DRW
  • SN74HC112DRFK

CAD (KiCad official)

  • Symbol: SN74HC112DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc112dr-etched.step / sn74hc112dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc112dr.step / sn74hc112dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 cded38abeff84d04, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF