Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74HC10PWR

Texas Instruments · Logic Gates · TSSOP-14

SN74HC10PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Channel 1 NAND gate input A; VI = 0 to VCC, input leakage max ±1 µA at VI = VCC or 0 V (VCC = 6 V); input capacitance max 10 pF.
2	1B	input	Channel 1 NAND gate input B; VI = 0 to VCC, input leakage max ±1 µA at VI = VCC or 0 V (VCC = 6 V); input capacitance max 10 pF.
3	2A	input	Channel 2 NAND gate input A; VI = 0 to VCC, input leakage max ±1 µA at VI = VCC or 0 V (VCC = 6 V); input capacitance max 10 pF.
4	2B	input	Channel 2 NAND gate input B; VI = 0 to VCC, input leakage max ±1 µA at VI = VCC or 0 V (VCC = 6 V); input capacitance max 10 pF.
5	2C	input	Channel 2 NAND gate input C; VI = 0 to VCC, input leakage max ±1 µA at VI = VCC or 0 V (VCC = 6 V); input capacitance max 10 pF.
6	2Y	output	Channel 2 NAND gate output Y = NOT(A·B·C); VOH min 4.4 V at VCC = 4.5 V, IOH = −20 µA; VOL max 0.1 V at VCC = 4.5 V, IOL = 20 µA; continuous output current max ±25 mA.
7	GND	power_in	Ground return for all internal logic and output stages; continuous current through GND pin max ±50 mA absolute maximum.
8	3Y	output	Channel 3 NAND gate output Y = NOT(A·B·C); VOH min 4.4 V at VCC = 4.5 V, IOH = −20 µA; VOL max 0.1 V at VCC = 4.5 V, IOL = 20 µA; continuous output current max ±25 mA.
9	3A	input	Channel 3 NAND gate input A; VI = 0 to VCC, input leakage max ±1 µA at VI = VCC or 0 V (VCC = 6 V); input capacitance max 10 pF.
10	3B	input	Channel 3 NAND gate input B; VI = 0 to VCC, input leakage max ±1 µA at VI = VCC or 0 V (VCC = 6 V); input capacitance max 10 pF.
11	3C	input	Channel 3 NAND gate input C; VI = 0 to VCC, input leakage max ±1 µA at VI = VCC or 0 V (VCC = 6 V); input capacitance max 10 pF.
12	1Y	output	Channel 1 NAND gate output Y = NOT(A·B·C); VOH min 4.4 V at VCC = 4.5 V, IOH = −20 µA; VOL max 0.1 V at VCC = 4.5 V, IOL = 20 µA; continuous output current max ±25 mA.
13	1C	input	Channel 1 NAND gate input C; VI = 0 to VCC, input leakage max ±1 µA at VI = VCC or 0 V (VCC = 6 V); input capacitance max 10 pF.
14	VCC	power_in	Positive supply voltage; recommended 2 V to 6 V, absolute maximum 7 V; ICC max 20 µA at no load (TA = 25°C, VCC = 6 V); continuous current through VCC max ±50 mA.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-14
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: SN74HC10PWR
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: sn74hc10pwr-etched.step / sn74hc10pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc10pwr.step / sn74hc10pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 e60b2aaf0e5b53f4, retrieved 2026-09-26, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF