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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74HC109DR

Texas Instruments · Flip Flops · SOP-16

SN74HC109DR from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	~1CLR	input	Active-low asynchronous clear for FF1; a low level overrides all other inputs and forces Q1 low and ~Q1 high regardless of clock state.
2	1J	input	J data input for FF1; sampled on the positive-going edge of 1CLK when ~1PRE and ~1CLR are both inactive (high); setup time 25 ns min at VCC = 4.5 V.
3	~1K	input	Active-low K input for FF1; sampled on the positive-going edge of 1CLK when ~1PRE and ~1CLR are both inactive (high); setup time 25 ns min at VCC = 4.5 V.
4	1CLK	input	Clock input for FF1; J and ~K data are transferred to outputs on the positive-going edge; maximum clock frequency 25 MHz at VCC = 4.5 V.
5	~1PRE	input	Active-low asynchronous preset for FF1; a low level forces Q1 high and ~Q1 low regardless of all other inputs.
6	1Q	output	Non-inverting output of FF1; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH/IOL = ±4 mA, VCC = 4.5 V.
7	~1Q	output	Inverting output of FF1; complementary to 1Q; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH/IOL = ±4 mA, VCC = 4.5 V.
8	GND	power_in	Ground reference; continuous current through GND pin ±70 mA absolute maximum.
9	~2Q	output	Inverting output of FF2; complementary to 2Q; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH/IOL = ±4 mA, VCC = 4.5 V.
10	2Q	output	Non-inverting output of FF2; VOH ≥ 3.84 V and VOL ≤ 0.33 V at IOH/IOL = ±4 mA, VCC = 4.5 V.
11	~2PRE	input	Active-low asynchronous preset for FF2; a low level forces 2Q high and ~2Q low regardless of all other inputs.
12	2CLK	input	Clock input for FF2; J and ~K data are transferred to outputs on the positive-going edge; maximum clock frequency 25 MHz at VCC = 4.5 V.
13	~2K	input	Active-low K input for FF2; sampled on the positive-going edge of 2CLK when ~2PRE and ~2CLR are both inactive (high); setup time 25 ns min at VCC = 4.5 V.
14	2J	input	J data input for FF2; sampled on the positive-going edge of 2CLK when ~2PRE and ~2CLR are both inactive (high); setup time 25 ns min at VCC = 4.5 V.
15	~2CLR	input	Active-low asynchronous clear for FF2; a low level overrides all other inputs and forces 2Q low and ~2Q high regardless of clock state.
16	VCC	power_in	Positive supply voltage; recommended operating range 2 V to 6 V; ICC 40 µA max at VCC = 6 V, IO = 0.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOP-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: SN74HC109DR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)
3D model files: sn74hc109dr-etched.step / sn74hc109dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc109dr.step / sn74hc109dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (25 pp, sha256 c19a2bd6168b9ac8, retrieved 2026-09-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF