component
SN74HC107DR
Public Made by Adomby adom
lingxingic Flip Flops, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74HC107DR
lingxingic · Flip Flops · SOP-14
SN74HC107DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1J | input | Synchronous J input of flip-flop 1, sampled on the HIGH-to-LOW transition of 1CP (see function table). |
| 2 | ~{1Q} | output | Complement output of flip-flop 1, the inverse of 1Q. |
| 3 | 1Q | output | True output of flip-flop 1. |
| 4 | 1K | input | Synchronous K input of flip-flop 1, sampled on the HIGH-to-LOW transition of 1CP (see function table). |
| 5 | 2Q | output | True output of flip-flop 2. |
| 6 | ~{2Q} | output | Complement output of flip-flop 2, the inverse of 2Q. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages. |
| 8 | 2J | input | Synchronous J input of flip-flop 2, sampled on the HIGH-to-LOW transition of 2CP (see function table). |
| 9 | 2CP | input | Clock input of flip-flop 2, triggered on the HIGH-to-LOW edge. |
| 10 | 2R | input | Asynchronous reset input of flip-flop 2, active LOW; it resets 2Q to LOW independent of the clock. |
| 11 | 2K | input | Synchronous K input of flip-flop 2, sampled on the HIGH-to-LOW transition of 2CP (see function table). |
| 12 | 1CP | input | Clock input of flip-flop 1, triggered on the HIGH-to-LOW edge. |
| 13 | 1R | input | Asynchronous reset input of flip-flop 1, active LOW; it resets 1Q to LOW independent of the clock. |
| 14 | VCC | power_in | Supply voltage; 2.0 V to 6.0 V for SN74HC107 (4.5 V to 5.5 V for the HCT variant), per recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 6 | ||
| Supply current (absolute maximum) | ICC | 50 | mA | 6 | |||
| Ground current (absolute maximum) | IGND | -50 | mA | 6 | |||
| Input clamping current (absolute maximum) | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 6 | |
| Output clamping current (absolute maximum) | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 6 | |
| Output current (absolute maximum) | IO | -25 | 25 | mA | -0.5V < VO < VCC+0.5V | 6 | |
| Storage temperature (absolute maximum) | Tstg | -65 | 150 | ℃ | 6 | ||
| Soldering temperature (absolute maximum) | TL | 260 | ℃ | 10s, SOP/TSSOP | 6 | ||
| Supply voltage (recommended, HC) | VCC | 2 | 5 | 6 | V | 6 | |
| Input voltage (recommended, HC) | VI | 0 | V | 6 | |||
| Output voltage (recommended, HC) | VO | 0 | V | 6 | |||
| Ambient temperature (recommended) | Tamb | -40 | 125 | ℃ | 6 | ||
| HIGH-level input voltage, VCC=2.0V | VIH | 1.5 | V | Tamb=-40℃ to +125℃ | 8 | ||
| HIGH-level input voltage, VCC=4.5V | VIH | 3.15 | V | Tamb=-40℃ to +125℃ | 8 | ||
| HIGH-level input voltage, VCC=6.0V | VIH | 4.2 | V | Tamb=-40℃ to +125℃ | 8 | ||
| LOW-level input voltage, VCC=2.0V | VIL | 0.5 | V | Tamb=-40℃ to +125℃ | 8 | ||
| LOW-level input voltage, VCC=4.5V | VIL | 1.35 | V | Tamb=-40℃ to +125℃ | 8 | ||
| LOW-level input voltage, VCC=6.0V | VIL | 1.8 | V | Tamb=-40℃ to +125℃ | 8 | ||
| HIGH-level output voltage, VCC=2.0V | VOH | 1.9 | V | Tamb=-40℃ to +125℃; IO=-20uA | 8 | ||
| HIGH-level output voltage, VCC=4.5V | VOH | 4.4 | V | Tamb=-40℃ to +125℃; IO=-20uA | 8 | ||
| HIGH-level output voltage, VCC=6.0V | VOH | 5.9 | V | Tamb=-40℃ to +125℃; IO=-20uA | 8 | ||
| HIGH-level output voltage, VCC=4.5V | VOH | 3.7 | V | Tamb=-40℃ to +125℃; IO=-4.0mA | 8 | ||
| HIGH-level output voltage, VCC=6.0V | VOH | 5.2 | V | Tamb=-40℃ to +125℃; IO=-5.2mA | 8 | ||
| LOW-level output voltage, VCC=2.0V | VOL | 0.1 | V | Tamb=-40℃ to +125℃; IO=20uA | 8 | ||
| LOW-level output voltage, VCC=4.5V | VOL | 0.1 | V | Tamb=-40℃ to +125℃; IO=20uA | 8 | ||
| LOW-level output voltage, VCC=6.0V | VOL | 0.1 | V | Tamb=-40℃ to +125℃; IO=20uA | 8 | ||
| LOW-level output voltage, VCC=4.5V | VOL | 0.4 | V | Tamb=-40℃ to +125℃; IO=4.0mA | 8 | ||
| LOW-level output voltage, VCC=6.0V | VOL | 0.4 | V | Tamb=-40℃ to +125℃; IO=5.2mA | 8 | ||
| Input leakage current, VCC=6.0V | II | -1 | 1 | uA | Tamb=-40℃ to +125℃; VI=VCC or GND | 8 | |
| Supply current, VCC=6.0V | ICC | 160 | uA | Tamb=-40℃ to +125℃; VI=VCC or GND; IO=0A | 8 | ||
| nCP to nQ propagation delay, VCC=2.0V | tPLH, tPHL | 240 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| nCP to nQ propagation delay, VCC=4.5V | tPLH, tPHL | 48 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| nCP to nQ propagation delay, VCC=6.0V | tPLH, tPHL | 41 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| nCP to nQ propagation delay (second listing), VCC=2.0V | tPLH, tPHL | 240 | ns | Tamb=-40℃ to +125℃; CL=50pF | 10 | ||
| nCP to nQ propagation delay (second listing), VCC=4.5V | tPLH, tPHL | 48 | ns | Tamb=-40℃ to +125℃; CL=50pF | 10 | ||
| nCP to nQ propagation delay (second listing), VCC=6.0V | tPLH, tPHL | 41 | ns | Tamb=-40℃ to +125℃; CL=50pF | 10 | ||
| nR to nQ/nQ propagation delay, VCC=2.0V | tPLH, tPHL | 235 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 | ||
| nR to nQ/nQ propagation delay, VCC=4.5V | tPLH, tPHL | 47 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 | ||
| Output transition time, VCC=2.0V | tTHL, tTLH | 110 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| Output transition time, VCC=4.5V | tTHL, tTLH | 22 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| nCP clock pulse width HIGH or LOW, VCC=2.0V | tw | 120 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| nCP clock pulse width HIGH or LOW, VCC=4.5V | tw | 24 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| nCP clock pulse width HIGH or LOW, VCC=6.0V | tw | 20 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 | ||
| nR pulse width HIGH, VCC=2.0V | tw | 120 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 | ||
| nR pulse width HIGH, VCC=4.5V | tw | 24 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 | ||
| nR pulse width HIGH, VCC=6.0V | tw | 20 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 11 | ||
| nR to nCP recovery time, VCC=2.0V | trec | 90 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 | ||
| nR to nCP recovery time, VCC=4.5V | trec | 18 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 | ||
| nR to nCP recovery time, VCC=6.0V | trec | 15 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 11 | ||
| nJ, nK to nCP set-up time, VCC=2.0V | tsu | 150 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| nJ, nK to nCP set-up time, VCC=4.5V | tsu | 30 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| nJ, nK to nCP set-up time, VCC=6.0V | tsu | 26 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 | ||
| nJ, nK to nCP hold time, VCC=2.0V | th | 3 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| nJ, nK to nCP hold time, VCC=4.5V | th | 3 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 | ||
| nJ, nK to nCP hold time, VCC=6.0V | th | 3 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 | ||
| Maximum clock frequency, VCC=2.0V | fmax | 4 | MHz | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 | ||
| Maximum clock frequency, VCC=4.5V | fmax | 20 | MHz | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 | ||
| Maximum clock frequency, VCC=6.0V | fmax | 24 | MHz | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 |
CAD (KiCad official)
- Symbol:
SN74HC107DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hc107dr-etched.step/sn74hc107dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc107dr.step/sn74hc107dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (18 pp, sha256
99a95eaa77126bd1, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HC107DR
**lingxingic** · Flip Flops · SOP-14
SN74HC107DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1J | input | Synchronous J input of flip-flop 1, sampled on the HIGH-to-LOW transition of 1CP (see function table). |
| 2 | ~{1Q} | output | Complement output of flip-flop 1, the inverse of 1Q. |
| 3 | 1Q | output | True output of flip-flop 1. |
| 4 | 1K | input | Synchronous K input of flip-flop 1, sampled on the HIGH-to-LOW transition of 1CP (see function table). |
| 5 | 2Q | output | True output of flip-flop 2. |
| 6 | ~{2Q} | output | Complement output of flip-flop 2, the inverse of 2Q. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages. |
| 8 | 2J | input | Synchronous J input of flip-flop 2, sampled on the HIGH-to-LOW transition of 2CP (see function table). |
| 9 | 2CP | input | Clock input of flip-flop 2, triggered on the HIGH-to-LOW edge. |
| 10 | 2R | input | Asynchronous reset input of flip-flop 2, active LOW; it resets 2Q to LOW independent of the clock. |
| 11 | 2K | input | Synchronous K input of flip-flop 2, sampled on the HIGH-to-LOW transition of 2CP (see function table). |
| 12 | 1CP | input | Clock input of flip-flop 1, triggered on the HIGH-to-LOW edge. |
| 13 | 1R | input | Asynchronous reset input of flip-flop 1, active LOW; it resets 1Q to LOW independent of the clock. |
| 14 | VCC | power_in | Supply voltage; 2.0 V to 6.0 V for SN74HC107 (4.5 V to 5.5 V for the HCT variant), per recommended operating conditions. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | | 7 | V | | 6 |
| Supply current (absolute maximum) | ICC | | | 50 | mA | | 6 |
| Ground current (absolute maximum) | IGND | -50 | | | mA | | 6 |
| Input clamping current (absolute maximum) | IIK | -20 | | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 6 |
| Output clamping current (absolute maximum) | IOK | -20 | | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 6 |
| Output current (absolute maximum) | IO | -25 | | 25 | mA | -0.5V < VO < VCC+0.5V | 6 |
| Storage temperature (absolute maximum) | Tstg | -65 | | 150 | ℃ | | 6 |
| Soldering temperature (absolute maximum) | TL | | | 260 | ℃ | 10s, SOP/TSSOP | 6 |
| Supply voltage (recommended, HC) | VCC | 2 | 5 | 6 | V | | 6 |
| Input voltage (recommended, HC) | VI | 0 | | | V | | 6 |
| Output voltage (recommended, HC) | VO | 0 | | | V | | 6 |
| Ambient temperature (recommended) | Tamb | -40 | | 125 | ℃ | | 6 |
| HIGH-level input voltage, VCC=2.0V | VIH | 1.5 | | | V | Tamb=-40℃ to +125℃ | 8 |
| HIGH-level input voltage, VCC=4.5V | VIH | 3.15 | | | V | Tamb=-40℃ to +125℃ | 8 |
| HIGH-level input voltage, VCC=6.0V | VIH | 4.2 | | | V | Tamb=-40℃ to +125℃ | 8 |
| LOW-level input voltage, VCC=2.0V | VIL | | | 0.5 | V | Tamb=-40℃ to +125℃ | 8 |
| LOW-level input voltage, VCC=4.5V | VIL | | | 1.35 | V | Tamb=-40℃ to +125℃ | 8 |
| LOW-level input voltage, VCC=6.0V | VIL | | | 1.8 | V | Tamb=-40℃ to +125℃ | 8 |
| HIGH-level output voltage, VCC=2.0V | VOH | 1.9 | | | V | Tamb=-40℃ to +125℃; IO=-20uA | 8 |
| HIGH-level output voltage, VCC=4.5V | VOH | 4.4 | | | V | Tamb=-40℃ to +125℃; IO=-20uA | 8 |
| HIGH-level output voltage, VCC=6.0V | VOH | 5.9 | | | V | Tamb=-40℃ to +125℃; IO=-20uA | 8 |
| HIGH-level output voltage, VCC=4.5V | VOH | 3.7 | | | V | Tamb=-40℃ to +125℃; IO=-4.0mA | 8 |
| HIGH-level output voltage, VCC=6.0V | VOH | 5.2 | | | V | Tamb=-40℃ to +125℃; IO=-5.2mA | 8 |
| LOW-level output voltage, VCC=2.0V | VOL | | | 0.1 | V | Tamb=-40℃ to +125℃; IO=20uA | 8 |
| LOW-level output voltage, VCC=4.5V | VOL | | | 0.1 | V | Tamb=-40℃ to +125℃; IO=20uA | 8 |
| LOW-level output voltage, VCC=6.0V | VOL | | | 0.1 | V | Tamb=-40℃ to +125℃; IO=20uA | 8 |
| LOW-level output voltage, VCC=4.5V | VOL | | | 0.4 | V | Tamb=-40℃ to +125℃; IO=4.0mA | 8 |
| LOW-level output voltage, VCC=6.0V | VOL | | | 0.4 | V | Tamb=-40℃ to +125℃; IO=5.2mA | 8 |
| Input leakage current, VCC=6.0V | II | -1 | | 1 | uA | Tamb=-40℃ to +125℃; VI=VCC or GND | 8 |
| Supply current, VCC=6.0V | ICC | | | 160 | uA | Tamb=-40℃ to +125℃; VI=VCC or GND; IO=0A | 8 |
| nCP to nQ propagation delay, VCC=2.0V | tPLH, tPHL | | | 240 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| nCP to nQ propagation delay, VCC=4.5V | tPLH, tPHL | | | 48 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| nCP to nQ propagation delay, VCC=6.0V | tPLH, tPHL | | | 41 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| nCP to nQ propagation delay (second listing), VCC=2.0V | tPLH, tPHL | | | 240 | ns | Tamb=-40℃ to +125℃; CL=50pF | 10 |
| nCP to nQ propagation delay (second listing), VCC=4.5V | tPLH, tPHL | | | 48 | ns | Tamb=-40℃ to +125℃; CL=50pF | 10 |
| nCP to nQ propagation delay (second listing), VCC=6.0V | tPLH, tPHL | | | 41 | ns | Tamb=-40℃ to +125℃; CL=50pF | 10 |
| nR to nQ/nQ propagation delay, VCC=2.0V | tPLH, tPHL | | | 235 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 |
| nR to nQ/nQ propagation delay, VCC=4.5V | tPLH, tPHL | | | 47 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 |
| Output transition time, VCC=2.0V | tTHL, tTLH | | | 110 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| Output transition time, VCC=4.5V | tTHL, tTLH | | | 22 | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| nCP clock pulse width HIGH or LOW, VCC=2.0V | tw | 120 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| nCP clock pulse width HIGH or LOW, VCC=4.5V | tw | 24 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| nCP clock pulse width HIGH or LOW, VCC=6.0V | tw | 20 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 |
| nR pulse width HIGH, VCC=2.0V | tw | 120 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 |
| nR pulse width HIGH, VCC=4.5V | tw | 24 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 |
| nR pulse width HIGH, VCC=6.0V | tw | 20 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 11 |
| nR to nCP recovery time, VCC=2.0V | trec | 90 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 |
| nR to nCP recovery time, VCC=4.5V | trec | 18 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 10 |
| nR to nCP recovery time, VCC=6.0V | trec | 15 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 5 | 11 |
| nJ, nK to nCP set-up time, VCC=2.0V | tsu | 150 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| nJ, nK to nCP set-up time, VCC=4.5V | tsu | 30 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| nJ, nK to nCP set-up time, VCC=6.0V | tsu | 26 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 |
| nJ, nK to nCP hold time, VCC=2.0V | th | 3 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| nJ, nK to nCP hold time, VCC=4.5V | th | 3 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 |
| nJ, nK to nCP hold time, VCC=6.0V | th | 3 | | | ns | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 |
| Maximum clock frequency, VCC=2.0V | fmax | 4 | | | MHz | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 10 |
| Maximum clock frequency, VCC=4.5V | fmax | 20 | | | MHz | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 |
| Maximum clock frequency, VCC=6.0V | fmax | 24 | | | MHz | Tamb=-40℃ to +125℃; CL=50pF; see Figure 4 | 11 |
## CAD (KiCad official)
- Symbol: `SN74HC107DR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74hc107dr-etched.step` / `sn74hc107dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc107dr.step` / `sn74hc107dr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603380564397879296) (18 pp, sha256 `99a95eaa77126bd1`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hc107dr-datasheet.pdf)