main
Ray sn74hc08dr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) c530d0b 21h ago
{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74hc08dr",
  "title": "SN74HC08DR",
  "brief": "Texas Instruments Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "sn74hc08dr"
  ],
  "component": {
    "mpn": "SN74HC08DR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Gates",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc08.pdf",
    "parts": {
      "symbol": "sn74hc08dr.kicad_sym",
      "footprint": "sn74hc08dr.kicad_mod",
      "model_3d": "sn74hc08dr-etched.glb",
      "model_3d_plain": "sn74hc08dr.glb",
      "model_3d_step": "sn74hc08dr-etched.step",
      "model_3d_step_plain": "sn74hc08dr.step",
      "lbr": "sn74hc08dr.lbr"
    },
    "distributor_links": {
      "digikey": "296-1191-2-ND",
      "lcsc": "C337768"
    },
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Channel 1, Input A. Standard high-impedance CMOS input to gate 1; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Must not be left floating."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Channel 1, Input B. Standard CMOS input to gate 1; combined with 1A to produce 1Y = 1A · 1B."
      },
      {
        "number": "3",
        "name": "1Y",
        "type": "output",
        "description": "Channel 1, Output Y. Balanced CMOS push-pull output; drives ±4 mA at VCC = 4.5 V while meeting VOH ≥ 3.84 V / VOL ≤ 0.33 V (-40 °C to 85 °C)."
      },
      {
        "number": "4",
        "name": "2A",
        "type": "input",
        "description": "Channel 2, Input A. Standard high-impedance CMOS input to gate 2."
      },
      {
        "number": "5",
        "name": "2B",
        "type": "input",
        "description": "Channel 2, Input B. Standard CMOS input to gate 2; combined with 2A to produce 2Y = 2A · 2B."
      },
      {
        "number": "6",
        "name": "2Y",
        "type": "output",
        "description": "Channel 2, Output Y. Balanced CMOS push-pull output for gate 2."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference. 0 V return for the logic core and output drivers; continuous current through VCC or GND is limited to ±50 mA (absolute max)."
      },
      {
        "number": "8",
        "name": "3Y",
        "type": "output",
        "description": "Channel 3, Output Y. Balanced CMOS push-pull output for gate 3."
      },
      {
        "number": "9",
        "name": "3A",
        "type": "input",
        "description": "Channel 3, Input A. Standard high-impedance CMOS input to gate 3."
      },
      {
        "number": "10",
        "name": "3B",
        "type": "input",
        "description": "Channel 3, Input B. Standard CMOS input to gate 3; combined with 3A to produce 3Y = 3A · 3B."
      },
      {
        "number": "11",
        "name": "4Y",
        "type": "output",
        "description": "Channel 4, Output Y. Balanced CMOS push-pull output for gate 4."
      },
      {
        "number": "12",
        "name": "4A",
        "type": "input",
        "description": "Channel 4, Input A. Standard high-impedance CMOS input to gate 4."
      },
      {
        "number": "13",
        "name": "4B",
        "type": "input",
        "description": "Channel 4, Input B. Standard CMOS input to gate 4; combined with 4A to produce 4Y = 4A · 4B."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply. Operating range 2 V to 6 V (5 V nominal); absolute maximum 7 V. Bypass locally to GND with a ceramic capacitor."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74hc08.pdf",
        "pages": 38,
        "sha256": "7c6d615e4510b91b",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -3.81
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HC08",
      "logic_family": "74HC",
      "function_code": "08",
      "function_class": "Gate",
      "function_name": "Quad 2-Input AND Gate",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "sn74hc08dr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74hc08dr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "108c6414b1a0fbfb9f34640a91708fea5c60127a68eb73e07a44c14ab92a4b22",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74hc08dr"
  ],
  "discovery_pitch": "SN74HC08DR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "sn74hc08dr.kicad_sym",
    "sn74hc08dr.kicad_mod",
    "sn74hc08dr.glb",
    "sn74hc08dr.step",
    "sn74hc08dr-etched.step",
    "sn74hc08dr.lbr",
    "docs/hero.png",
    "docs/sn74hc08dr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "SN74HC08DRD",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRDB",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRDBR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRN",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRNS",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRNSR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRPW",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRPWR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRFK",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRJ",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC08DRW",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-25T06:57:51.572Z"
}