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SN74HC08DR-JSM
Public Made by Adomby adom
JSMSEMI Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74HC08DR-JSM
JSMSEMI · Logic Gates · SOP-14
SN74HC08DR-JSM from JSMSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of gate 1 (2-input AND). |
| 2 | 1B | input | Data input B of gate 1 (2-input AND). |
| 3 | 1Y | output | Data output of gate 1. |
| 4 | 2A | input | Data input A of gate 2 (2-input AND). |
| 5 | 2B | input | Data input B of gate 2 (2-input AND). |
| 6 | 2Y | output | Data output of gate 2; the pin table labels it 'input/output', but the logic diagram shows it as an output. |
| 7 | GND | power_in | Ground (0V). |
| 8 | 3Y | output | Data output of gate 3. |
| 9 | 3A | input | Data input A of gate 3 (2-input AND). |
| 10 | 3B | input | Data input B of gate 3 (2-input AND). |
| 11 | 4Y | output | Data output of gate 4. |
| 12 | 4A | input | Data input A of gate 4 (2-input AND). |
| 13 | 4B | input | Data input B of gate 4 (2-input AND). |
| 14 | Vcc | power_in | Supply voltage; recommended 2.0V to 6.0V (5.0V typ), absolute maximum -0.5V to +7V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74HC08DR-JSM - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hc08dr-jsm-etched.step/sn74hc08dr-jsm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc08dr-jsm.step/sn74hc08dr-jsm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JSMSEMI datasheet (6 pp, sha256
473235a01a719dc5, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HC08DR-JSM
**JSMSEMI** · Logic Gates · SOP-14
SN74HC08DR-JSM from JSMSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of gate 1 (2-input AND). |
| 2 | 1B | input | Data input B of gate 1 (2-input AND). |
| 3 | 1Y | output | Data output of gate 1. |
| 4 | 2A | input | Data input A of gate 2 (2-input AND). |
| 5 | 2B | input | Data input B of gate 2 (2-input AND). |
| 6 | 2Y | output | Data output of gate 2; the pin table labels it 'input/output', but the logic diagram shows it as an output. |
| 7 | GND | power_in | Ground (0V). |
| 8 | 3Y | output | Data output of gate 3. |
| 9 | 3A | input | Data input A of gate 3 (2-input AND). |
| 10 | 3B | input | Data input B of gate 3 (2-input AND). |
| 11 | 4Y | output | Data output of gate 4. |
| 12 | 4A | input | Data input A of gate 4 (2-input AND). |
| 13 | 4B | input | Data input B of gate 4 (2-input AND). |
| 14 | Vcc | power_in | Supply voltage; recommended 2.0V to 6.0V (5.0V typ), absolute maximum -0.5V to +7V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `SN74HC08DR-JSM`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74hc08dr-jsm-etched.step` / `sn74hc08dr-jsm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc08dr-jsm.step` / `sn74hc08dr-jsm.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [JSMSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603080342299557888) (6 pp, sha256 `473235a01a719dc5`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hc08dr-jsm-datasheet.pdf)