Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Made with kicad-footprint-generator 10.0 · KiCad file format 20260206

Name	Last commit message	Last updated
docs	sn74hc08: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	4d ago
viewers	interactive viewers · Ray	1mo ago
package.json	Publish 0.1.0 · Ray	1mo ago
page.json	sn74hc08: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	16h ago
README.md	sn74hc08: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	16d ago
sn74hc08-etched.fit.json	sn74hc08: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	4d ago
sn74hc08-etched.glb	sn74hc08: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	4d ago
sn74hc08-etched.step	sn74hc08: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	4d ago
SN74HC08.adom-lbr.json	SN74HC08: validated Fusion/EAGLE library + adom-lbr hub, generated from this page's KiCad sources · Ray	1mo ago
sn74hc08.glb	Publish 0.1.0 · Ray	1mo ago
sn74hc08.kicad_mod	Publish 0.1.0 · Ray	1mo ago
sn74hc08.kicad_sym	Publish 0.1.0 · Ray	1mo ago
sn74hc08.lbr	add validated EAGLE .lbr (Fusion library) · Ray	1mo ago
SN74HC08.lbr	SN74HC08: validated Fusion/EAGLE library + adom-lbr hub, generated from this page's KiCad sources · Ray	1mo ago
sn74hc08.step	add .step (Fusion 3D source) · Ray	1mo ago

SN74HC08

Texas Instruments · Logic Gate · SOIC-14

The SN74HC08 contains four independent 2-input AND gates in the 74HC CMOS logic family. Each output goes high only when both inputs are high, useful for gating clocks and enables, combining flags, and general glue logic.

Pinout

Pin	Name	Type	Function
1	1A	input	Channel 1, Input A. Logic input to gate 1 (buffered CMOS input). V_IH ≥ 3.15 V at V_CC = 4.5 V; input leakage ±0.1 µA typ.
2	1B	input	Channel 1, Input B. Logic input to gate 1 (buffered CMOS input).
3	1Y	output	Channel 1, Output Y. AND output: Y = 1A · 1B. Drives up to ±4 mA at V_CC = 4.5 V with V_OH ≥ 3.98 V / V_OL ≤ 0.26 V.
4	2A	input	Channel 2, Input A. Logic input to gate 2.
5	2B	input	Channel 2, Input B. Logic input to gate 2.
6	2Y	output	Channel 2, Output Y. AND output: Y = 2A · 2B.
7	GND	power_in	Ground reference (0 V). Common return for V_CC.
8	3Y	output	Channel 3, Output Y. AND output: Y = 3A · 3B.
9	3A	input	Channel 3, Input A. Logic input to gate 3.
10	3B	input	Channel 3, Input B. Logic input to gate 3.
11	4Y	output	Channel 4, Output Y. AND output: Y = 4A · 4B.
12	4A	input	Channel 4, Input A. Logic input to gate 4.
13	4B	input	Channel 4, Input B. Logic input to gate 4.
14	VCC	power_in	Positive supply. Operating range 2 V to 6 V (recommended); absolute max 7 V.

Key specifications

Parameter	Value
Type	Quad 2-input AND gate
Logic family	74HC (CMOS)
Supply voltage	2 V to 6 V
Output current	+-5.2 mA at VCC = 4.5 V
Propagation delay	8 ns typ at 5 V
Operating temperature	-40 C to 85 C

Ordering variants

Same part, different packaging or reel option.

SN74HC08D
SN74HC08DB
SN74HC08N
SN74HC08NS
SN74HC08PW
SN74HC08FK
SN74HC08J
SN74HC08W

CAD (KiCad official)

Symbol: sn74hc08.kicad_sym
Footprint: sn74hc08.kicad_mod
3D model: SOIC-14 body from KiCad Package_SO/SOIC-14_3.9x8.7mm_P1.27mm.
3D model files: sn74hc08-etched.step / sn74hc08-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc08.step / sn74hc08.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (38 pp, sha256 7c6d615e4510b91b, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SN74HC08 Quad AND Gate