component
SN74HC02QPWRQ1
Public Made by Adomby adom
Texas Instruments Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74HC02QPWRQ1
Texas Instruments · Gates · TSSOP-14
SN74HC02QPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Channel 1 output Y of the 2-input NOR gate (Y = A + B), with balanced CMOS push-pull drive. |
| 2 | 1A | input | Channel 1 input A; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 3 | 1B | input | Channel 1 input B; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 4 | 2Y | output | Channel 2 output Y of the 2-input NOR gate (Y = A + B), with balanced CMOS push-pull drive. |
| 5 | 2A | input | Channel 2 input A; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 6 | 2B | input | Channel 2 input B; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 7 | GND | power_in | Ground; continuous current through GND or VCC is limited to ±50 mA. |
| 8 | 3A | input | Channel 3 input A; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 9 | 3B | input | Channel 3 input B; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 10 | 3Y | output | Channel 3 output Y of the 2-input NOR gate (Y = A + B), with balanced CMOS push-pull drive. |
| 11 | 4A | input | Channel 4 input A; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 12 | 4B | input | Channel 4 input B; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 13 | 4Y | output | Channel 4 output Y of the 2-input NOR gate (Y = A + B), with balanced CMOS push-pull drive. |
| 14 | VCC | power_in | Positive supply, recommended 2 V to 6 V (absolute max 7 V), with a 0.1 µF bypass capacitor recommended close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 3 | |
| Continuous output current | IO | -25 | 25 | mA | VO = 0 to VCC | 3 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 3 | |||
| Junction temperature | TJ | 150 | °C | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human body model, AEC Q100-002 | 4 | |
| ESD CDM | V(ESD) | -1000 | 1000 | V | Charged device model, AEC Q100-011 | 4 | |
| Supply voltage | VCC | 2 | 5 | 6 | V | 4 | |
| High-level input voltage | VIH | 1.5 | V | VCC = 2 V | 4 | ||
| High-level input voltage | VIH | 3.15 | V | VCC = 4.5 V | 4 | ||
| High-level input voltage | VIH | 4.2 | V | VCC = 6 V | 4 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC = 2 V | 4 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC = 4.5 V | 4 | ||
| Low-level input voltage | VIL | 1.8 | V | VCC = 6 V | 4 | ||
| Input voltage | VI | 0 | 6 | V | Max printed as VCC | 4 | |
| Output voltage | VO | 0 | 6 | V | Max printed as VCC | 4 | |
| Input transition rise and fall rate | Δt/Δv | 1000 | ns | VCC = 2 V | 4 | ||
| Input transition rise and fall rate | Δt/Δv | 500 | ns | VCC = 4.5 V | 4 | ||
| Input transition rise and fall rate | Δt/Δv | 400 | ns | VCC = 6 V | 4 | ||
| Operating free-air temperature | TA | -40 | 125 | °C | SN74HC02-Q1 | 4 | |
| High-level output voltage | VOH | 1.9 | V | VI = VIH or VIL, IOH = -20 µA, VCC = 2 V, TA = -40°C to 125°C | 5 | ||
| High-level output voltage | VOH | 4.4 | V | VI = VIH or VIL, IOH = -20 µA, VCC = 4.5 V, TA = -40°C to 125°C | 5 | ||
| High-level output voltage | VOH | 5.9 | V | VI = VIH or VIL, IOH = -20 µA, VCC = 6 V, TA = -40°C to 125°C | 5 | ||
| High-level output voltage | VOH | 3.7 | V | VI = VIH or VIL, IOH = -4 mA, VCC = 4.5 V, TA = -40°C to 125°C | 5 | ||
| High-level output voltage | VOH | 5.2 | V | VI = VIH or VIL, IOH = -5.2 mA, VCC = 6 V, TA = -40°C to 125°C | 5 | ||
| Low-level output voltage | VOL | 0.1 | V | VI = VIH or VIL, IOL = 20 µA, VCC = 2 V, TA = -40°C to 125°C | 5 | ||
| Low-level output voltage | VOL | 0.4 | V | VI = VIH or VIL, IOL = 4 mA, VCC = 4.5 V, TA = -40°C to 125°C | 5 | ||
| Input leakage current | II | -1000 | 1000 | nA | VI = VCC or 0, VCC = 6 V, TA = -40°C to 125°C | 5 | |
| Supply current | ICC | 40 | µA | VI = VCC or 0, IO = 0, VCC = 6 V, TA = -40°C to 125°C | 5 | ||
| Input capacitance | Ci | 3 | 10 | pF | VCC = 2 V to 6 V | 5 | |
| Propagation delay A or B to Y | tpd | 135 | ns | VCC = 2 V, CL = 50 pF, TA = -40°C to 125°C | 5 | ||
| Propagation delay A or B to Y | tpd | 27 | ns | VCC = 4.5 V, CL = 50 pF, TA = -40°C to 125°C | 5 | ||
| Propagation delay A or B to Y | tpd | 23 | ns | VCC = 6 V, CL = 50 pF, TA = -40°C to 125°C | 5 | ||
| Transition time Y | tt | 110 | ns | VCC = 2 V, CL = 50 pF, TA = -40°C to 125°C | 5 | ||
| Transition time Y | tt | 22 | ns | VCC = 4.5 V, CL = 50 pF, TA = -40°C to 125°C | 5 | ||
| Transition time Y | tt | 19 | ns | VCC = 6 V, CL = 50 pF, TA = -40°C to 125°C | 5 | ||
| Power dissipation capacitance per gate | Cpd | 22 | pF | No load | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 151.7 | °C/W | PW (TSSOP) 14 pins | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 79.4 | °C/W | PW (TSSOP) 14 pins | 4 | ||
| Junction-to-board thermal resistance | RθJB | 94.7 | °C/W | PW (TSSOP) 14 pins | 4 | ||
| Junction-to-top characterization parameter | ΨJT | 25.2 | °C/W | PW (TSSOP) 14 pins | 4 | ||
| Junction-to-board characterization parameter | ΨJB | 94.1 | °C/W | PW (TSSOP) 14 pins | 4 |
CAD (KiCad official)
- Symbol:
SN74HC02QPWRQ1 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hc02qpwrq1-etched.step/sn74hc02qpwrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc02qpwrq1.step/sn74hc02qpwrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
c73698878c82bfa7, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HC02QPWRQ1
**Texas Instruments** · Gates · TSSOP-14
SN74HC02QPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Channel 1 output Y of the 2-input NOR gate (Y = A + B), with balanced CMOS push-pull drive. |
| 2 | 1A | input | Channel 1 input A; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 3 | 1B | input | Channel 1 input B; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 4 | 2Y | output | Channel 2 output Y of the 2-input NOR gate (Y = A + B), with balanced CMOS push-pull drive. |
| 5 | 2A | input | Channel 2 input A; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 6 | 2B | input | Channel 2 input B; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 7 | GND | power_in | Ground; continuous current through GND or VCC is limited to ±50 mA. |
| 8 | 3A | input | Channel 3 input A; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 9 | 3B | input | Channel 3 input B; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 10 | 3Y | output | Channel 3 output Y of the 2-input NOR gate (Y = A + B), with balanced CMOS push-pull drive. |
| 11 | 4A | input | Channel 4 input A; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 12 | 4B | input | Channel 4 input B; unused inputs must be tied to VCC or GND, and the input must stay within 0 to VCC. |
| 13 | 4Y | output | Channel 4 output Y of the 2-input NOR gate (Y = A + B), with balanced CMOS push-pull drive. |
| 14 | VCC | power_in | Positive supply, recommended 2 V to 6 V (absolute max 7 V), with a 0.1 µF bypass capacitor recommended close to the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0 or VI > VCC | 3 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VCC | 3 |
| Continuous output current | IO | -25 | | 25 | mA | VO = 0 to VCC | 3 |
| Continuous current through VCC or GND | | -50 | | 50 | mA | | 3 |
| Junction temperature | TJ | | | 150 | °C | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| ESD HBM | V(ESD) | -2000 | | 2000 | V | Human body model, AEC Q100-002 | 4 |
| ESD CDM | V(ESD) | -1000 | | 1000 | V | Charged device model, AEC Q100-011 | 4 |
| Supply voltage | VCC | 2 | 5 | 6 | V | | 4 |
| High-level input voltage | VIH | 1.5 | | | V | VCC = 2 V | 4 |
| High-level input voltage | VIH | 3.15 | | | V | VCC = 4.5 V | 4 |
| High-level input voltage | VIH | 4.2 | | | V | VCC = 6 V | 4 |
| Low-level input voltage | VIL | | | 0.5 | V | VCC = 2 V | 4 |
| Low-level input voltage | VIL | | | 1.35 | V | VCC = 4.5 V | 4 |
| Low-level input voltage | VIL | | | 1.8 | V | VCC = 6 V | 4 |
| Input voltage | VI | 0 | | 6 | V | Max printed as VCC | 4 |
| Output voltage | VO | 0 | | 6 | V | Max printed as VCC | 4 |
| Input transition rise and fall rate | Δt/Δv | | | 1000 | ns | VCC = 2 V | 4 |
| Input transition rise and fall rate | Δt/Δv | | | 500 | ns | VCC = 4.5 V | 4 |
| Input transition rise and fall rate | Δt/Δv | | | 400 | ns | VCC = 6 V | 4 |
| Operating free-air temperature | TA | -40 | | 125 | °C | SN74HC02-Q1 | 4 |
| High-level output voltage | VOH | 1.9 | | | V | VI = VIH or VIL, IOH = -20 µA, VCC = 2 V, TA = -40°C to 125°C | 5 |
| High-level output voltage | VOH | 4.4 | | | V | VI = VIH or VIL, IOH = -20 µA, VCC = 4.5 V, TA = -40°C to 125°C | 5 |
| High-level output voltage | VOH | 5.9 | | | V | VI = VIH or VIL, IOH = -20 µA, VCC = 6 V, TA = -40°C to 125°C | 5 |
| High-level output voltage | VOH | 3.7 | | | V | VI = VIH or VIL, IOH = -4 mA, VCC = 4.5 V, TA = -40°C to 125°C | 5 |
| High-level output voltage | VOH | 5.2 | | | V | VI = VIH or VIL, IOH = -5.2 mA, VCC = 6 V, TA = -40°C to 125°C | 5 |
| Low-level output voltage | VOL | | | 0.1 | V | VI = VIH or VIL, IOL = 20 µA, VCC = 2 V, TA = -40°C to 125°C | 5 |
| Low-level output voltage | VOL | | | 0.4 | V | VI = VIH or VIL, IOL = 4 mA, VCC = 4.5 V, TA = -40°C to 125°C | 5 |
| Input leakage current | II | -1000 | | 1000 | nA | VI = VCC or 0, VCC = 6 V, TA = -40°C to 125°C | 5 |
| Supply current | ICC | | | 40 | µA | VI = VCC or 0, IO = 0, VCC = 6 V, TA = -40°C to 125°C | 5 |
| Input capacitance | Ci | | 3 | 10 | pF | VCC = 2 V to 6 V | 5 |
| Propagation delay A or B to Y | tpd | | | 135 | ns | VCC = 2 V, CL = 50 pF, TA = -40°C to 125°C | 5 |
| Propagation delay A or B to Y | tpd | | | 27 | ns | VCC = 4.5 V, CL = 50 pF, TA = -40°C to 125°C | 5 |
| Propagation delay A or B to Y | tpd | | | 23 | ns | VCC = 6 V, CL = 50 pF, TA = -40°C to 125°C | 5 |
| Transition time Y | tt | | | 110 | ns | VCC = 2 V, CL = 50 pF, TA = -40°C to 125°C | 5 |
| Transition time Y | tt | | | 22 | ns | VCC = 4.5 V, CL = 50 pF, TA = -40°C to 125°C | 5 |
| Transition time Y | tt | | | 19 | ns | VCC = 6 V, CL = 50 pF, TA = -40°C to 125°C | 5 |
| Power dissipation capacitance per gate | Cpd | | 22 | | pF | No load | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 151.7 | | °C/W | PW (TSSOP) 14 pins | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 79.4 | | °C/W | PW (TSSOP) 14 pins | 4 |
| Junction-to-board thermal resistance | RθJB | | 94.7 | | °C/W | PW (TSSOP) 14 pins | 4 |
| Junction-to-top characterization parameter | ΨJT | | 25.2 | | °C/W | PW (TSSOP) 14 pins | 4 |
| Junction-to-board characterization parameter | ΨJB | | 94.1 | | °C/W | PW (TSSOP) 14 pins | 4 |
## CAD (KiCad official)
- Symbol: `SN74HC02QPWRQ1`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74hc02qpwrq1-etched.step` / `sn74hc02qpwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc02qpwrq1.step` / `sn74hc02qpwrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hc02-q1) (23 pp, sha256 `c73698878c82bfa7`, retrieved 2026-10-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hc02qpwrq1-datasheet.pdf)