component
SN74HC02DR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC02DR
Texas Instruments · Logic Gates · SOIC-14
SN74HC02DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Output Y of Channel 1 NOR gate (Y = A + B); drives 0 to VCC V logic levels with fanout up to 10 LSTTL loads. |
| 2 | 1A | input | Input A to Channel 1 NOR gate; accepts 0 to VCC V logic levels with high-impedance CMOS input structure. |
| 3 | 1B | input | Input B to Channel 1 NOR gate; accepts 0 to VCC V logic levels with high-impedance CMOS input structure. |
| 4 | 2Y | output | Output Y of Channel 2 NOR gate (Y = A + B); drives 0 to VCC V logic levels with fanout up to 10 LSTTL loads. |
| 5 | 2A | input | Input A to Channel 2 NOR gate; accepts 0 to VCC V logic levels with high-impedance CMOS input structure. |
| 6 | 2B | input | Input B to Channel 2 NOR gate; accepts 0 to VCC V logic levels with high-impedance CMOS input structure. |
| 7 | GND | power_in | Ground (0 V reference); continuous current through VCC or GND limited to ±50 mA maximum. |
| 8 | 3A | input | Input A to Channel 3 NOR gate; accepts 0 to VCC V logic levels with high-impedance CMOS input structure. |
| 9 | 3B | input | Input B to Channel 3 NOR gate; accepts 0 to VCC V logic levels with high-impedance CMOS input structure. |
| 10 | 3Y | output | Output Y of Channel 3 NOR gate (Y = A + B); drives 0 to VCC V logic levels with fanout up to 10 LSTTL loads. |
| 11 | 4A | input | Input A to Channel 4 NOR gate; accepts 0 to VCC V logic levels with high-impedance CMOS input structure. |
| 12 | 4B | input | Input B to Channel 4 NOR gate; accepts 0 to VCC V logic levels with high-impedance CMOS input structure. |
| 13 | 4Y | output | Output Y of Channel 4 NOR gate (Y = A + B); drives 0 to VCC V logic levels with fanout up to 10 LSTTL loads. |
| 14 | VCC | power_in | Positive power supply; 2 V to 6 V operating range; continuous current through VCC or GND limited to ±50 mA maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74HC02DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hc02dr-etched.step/sn74hc02dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc02dr.step/sn74hc02dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (43 pp, sha256
8bcf9d8c4071beff, retrieved 2026-09-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).