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SN74GTLPH306PWR

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Texas Instruments Translators, Level Shifters, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74GTLPH306PWR

Texas Instruments · Translators, Level Shifters · TSSOP-24

SN74GTLPH306PWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable, LVTTL and 5-V tolerant; high puts the outputs in the high-impedance state (isolation), and it should be tied to VCC through a pullup resistor to ensure high impedance above 1.5 V VCC.
2 VCC power_in Supply voltage, 3.15 V to 3.45 V recommended (3.3 V nominal).
3 A1 bidirectional A-port channel 1 LVTTL I/O, 5-V tolerant, with bus hold on the data input and -24 mA/24 mA output drive.
4 A2 bidirectional A-port channel 2 LVTTL I/O, 5-V tolerant, with bus hold on the data input and -24 mA/24 mA output drive.
5 A3 bidirectional A-port channel 3 LVTTL I/O, 5-V tolerant, with bus hold on the data input and -24 mA/24 mA output drive.
6 A4 bidirectional A-port channel 4 LVTTL I/O, 5-V tolerant, with bus hold on the data input and -24 mA/24 mA output drive.
7 GND power_in Ground.
8 A5 bidirectional A-port channel 5 LVTTL I/O, 5-V tolerant, with bus hold on the data input and -24 mA/24 mA output drive.
9 A6 bidirectional A-port channel 6 LVTTL I/O, 5-V tolerant, with bus hold on the data input and -24 mA/24 mA output drive.
10 A7 bidirectional A-port channel 7 LVTTL I/O, 5-V tolerant, with bus hold on the data input and -24 mA/24 mA output drive.
11 A8 bidirectional A-port channel 8 LVTTL I/O, 5-V tolerant, with bus hold on the data input and -24 mA/24 mA output drive.
12 GND power_in Ground.
13 GND power_in Ground.
14 B8 bidirectional B-port channel 8 GTLP I/O with medium-drive 50 mA output.
15 B7 bidirectional B-port channel 7 GTLP I/O with medium-drive 50 mA output.
16 B6 bidirectional B-port channel 6 GTLP I/O with medium-drive 50 mA output.
17 B5 bidirectional B-port channel 5 GTLP I/O with medium-drive 50 mA output.
18 GND power_in Ground.
19 B4 bidirectional B-port channel 4 GTLP I/O with medium-drive 50 mA output.
20 B3 bidirectional B-port channel 3 GTLP I/O with medium-drive 50 mA output.
21 B2 bidirectional B-port channel 2 GTLP I/O with medium-drive 50 mA output.
22 B1 bidirectional B-port channel 1 GTLP I/O with medium-drive 50 mA output.
23 VREF power_in B-port differential input reference voltage, 0.87 V to 1.1 V for GTLP (0.74 V to 0.87 V for GTL), normally two-thirds VTT.
24 DIR input Direction control, LVTTL and 5-V tolerant; high transmits A to B and low transmits B to A when OE is low.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Logic
Pins 24

CAD (KiCad official)

  • Symbol: SN74GTLPH306PWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: sn74gtlph306pwr-etched.step / sn74gtlph306pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74gtlph306pwr.step / sn74gtlph306pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 6d1ae900f35582d6, retrieved 2026-10-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF