component

SN74GTLP1395PWR

Public Made by Adom

by adom

Texas Instruments Translators, Level Shifters, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74gtlp1395pwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 16d ago
viewers sn74gtlp1395pwr: viewers · Ray 16d ago
package.json sn74gtlp1395pwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray 7d ago
page.json sn74gtlp1395pwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray 7d ago
README.md Publish 0.1.0 · Ray 16d ago
sn74gtlp1395pwr-etched.glb sn74gtlp1395pwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray 7d ago
sn74gtlp1395pwr-etched.step sn74gtlp1395pwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray 7d ago
sn74gtlp1395pwr-hero.glb sn74gtlp1395pwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray 7d ago
sn74gtlp1395pwr-hero.overlay.json sn74gtlp1395pwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray 7d ago
sn74gtlp1395pwr.glb Publish 0.1.0 · Ray 16d ago
sn74gtlp1395pwr.kicad_mod Publish 0.1.0 · Ray 16d ago
sn74gtlp1395pwr.kicad_sym Publish 0.1.0 · Ray 16d ago
sn74gtlp1395pwr.lbr Publish 0.1.0 · Ray 16d ago
sn74gtlp1395pwr.step Publish 0.1.0 · Ray 16d ago

SN74GTLP1395PWR

Texas Instruments · Translators, Level Shifters · TSSOP-20

SN74GTLP1395PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y output Split-port LVTTL feedback output for channel 1; it is active when 1OEBY is low and disabled when 1OEBY is high.
2 1T/C input Polarity control for channel 1: high selects true data transmission, and low selects complementary (inverted) transmission in both directions.
3 2Y output Split-port LVTTL feedback output for channel 2; it is active when 2OEBY is low and disabled when 2OEBY is high.
4 GND power_in Ground reference pin.
5 1OEAB input Output-enable for the channel 1 B port; the B-port output is active when low and disabled when high.
6 VCC power_in Supply pin; when VCC is between 0 and 1.5 V the outputs are high-impedance, and OE should be pulled up to VCC to keep the high-impedance state above 1.5 V.
7 1A input LVTTL data input for channel 1; the LVTTL interfaces are 5-V tolerant.
8 GND power_in Ground reference pin.
9 2A input LVTTL data input for channel 2; the LVTTL interfaces are 5-V tolerant.
10 2OEAB input Output-enable for the channel 2 B port; the B-port output is active when low and disabled when high.
11 BIAS VCC power_in Precharges and preconditions the B-port input/output connections to prevent disturbance of active backplane data during card insertion or removal.
12 VREF power_in B-port differential input reference voltage.
13 GND power_in Ground reference pin.
14 2B bidirectional Channel 2 GTLP bus I/O (B port), which normally operates at GTLP signal levels.
15 ERC input Edge-rate control input: a high selects slow and a low selects fast B-port output rise and fall times.
16 1B bidirectional Channel 1 GTLP bus I/O (B port), which normally operates at GTLP signal levels.
17 GND power_in Ground reference pin.
18 2OEBY input Output-enable for the channel 2 Y output; the Y output is active when low and disabled when high.
19 2T/C input Polarity control for channel 2: high selects true data transmission, and low selects complementary (inverted) transmission in both directions.
20 1OEBY input Output-enable for the channel 1 Y output; the Y output is active when low and disabled when high.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74GTLP1395PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74gtlp1395pwr-etched.step / sn74gtlp1395pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74gtlp1395pwr.step / sn74gtlp1395pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 274d732aedb6b5ae, retrieved 2026-10-12, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF